Displaying 4 results from an estimated 4 matches for "v64f32".
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v4f32
2017 Aug 07
3
VBROADCAST Implementation Issues
..."GATHER_256B\t{$src2, {$dst} {${mask}}|${dst}
{${mask}}, $src2}",
[(set VR_2048:$dst, VK64WM:$mask_wb, (v64i32
(masked_gather (VR_2048:$src1), VK64WM:$mask,
addr:$src2)))],
IIC_MOV_MEM>, TA;
def: Pat<(v64f32 (masked_gather (VR_2048:$src1),
(VK64WM:$mask),(addr:$src2))), (GATHER_256B VR_2048:$src1, VK64WM:$mask,
addr:$src2)>;
Now getting this error:
llvm-tblgen: /utils/TableGen/X86RecognizableInstr.cpp:687: void
llvm::X86Disassembler::RecognizableInstr::emitInstructionSpecifier():
Assertion `numPh...
2017 Aug 07
2
VBROADCAST Implementation Issues
..."GATHER_256B\t{$src2, {$dst}{${mask}}|${dst} {${mask}},
$src2}"),
[(set VR_2048:$dst, _.KRCWM:$mask_wb, (v64i32
(GatherNode (VR_2048:$src1), _.KRCWM:$mask,
VR_2048:$src2))],
IIC_MOV_MEM>, TA;
def: Pat<(v64f32 (GatherNode addr:$src2)), (GATHER_256B addr:$src2)>;
Thank You
On Mon, Aug 7, 2017 at 2:57 AM, Craig Topper <craig.topper at gmail.com> wrote:
> masked_gather returns two results. The data and the modified mask. Note
> the $dst and the $mask_wb in the pattern below.
>
> mult...
2017 Aug 06
2
VBROADCAST Implementation Issues
...ollowing code.
def GATHER_256B : I<0x68, MRMSrcMem, (outs VR_2048:$dst), (ins
i2048mem:$src),
"GATHER_256B\t{$src, $dst|$dst, $src}",
[(set VR_2048:$dst, (v64i32 (masked_gather
addr:$src)))],
IIC_MOV_MEM>, TA;
def: Pat<(v64f32 (masked_gather addr:$src)), (GATHER_256B addr:$src)>;
Also i wrote this line in isellowering.h
setOperationAction(ISD::MGATHER, MVT::v64i32,
Legal);
But I am getting following error:
llvm-tblgen: /utils/TableGen/CodeGenDAGPatterns.cpp:2134:
llvm::TreePatternNode *ll...
2018 Apr 10
1
64 bit mask in x86vshuffle instruction
...them and
// lower them. Each lowering routine of a given type is allowed to assume
that
// the requisite ISA extensions for that element type are available.
switch (VT.SimpleTy) {
case MVT::v32f64:
return lowerV32F64VectorShuffle(DL, Mask, Zeroable, V1, V2, Subtarget,
DAG);
case MVT::v64f32:
return lowerV64F32VectorShuffle(DL, Mask, Zeroable, V1, V2, Subtarget,
DAG);
case MVT::v32i64:
return lowerV32I64VectorShuffle(DL, Mask, Zeroable, V1, V2, Subtarget,
DAG);
case MVT::v64i32:
return lowerV64I32VectorShuffle(DL, Mask, Zeroable, V1, V2, Subtarget,
DAG);
default:...