Displaying 6 results from an estimated 6 matches for "v512i16".
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v1i16
2018 Jan 17
3
Does it make sense to upstream some MVT's?
...at isn't used by current
backends in tree isn't great.
These are the MVT's that we have added:
16x16 element (2D SIMD) 1-bit predicate registers:
v256i1
16x16 element (2D SIMD) 16-bit registers:
v256i16
20x20 element (2D SIMD) 16-bit registers: (we round up to v512 instead of
v400):
v512i16
32-bit versions of the above 16-bit registers (to represent 32-bit
accumulators for MAD instructions and also dual-issue "wide" instructions
to the dual non-MAD ALU's in each lane)
v256i32
v512i32
For those interested in more details about Pixel Visual Core, the 6th
edition of Henn...
2018 Jan 17
0
Does it make sense to upstream some MVT's?
...ed by current backends in tree isn't great.
These are the MVT's that we have added:
16x16 element (2D SIMD) 1-bit predicate registers:
v256i1
16x16 element (2D SIMD) 16-bit registers:
v256i16
20x20 element (2D SIMD) 16-bit registers: (we round up to v512 instead of v400):
v512i16
32-bit versions of the above 16-bit registers (to represent 32-bit accumulators for MAD instructions and also dual-issue "wide" instructions to the dual non-MAD ALU's in each lane)
v256i32
v512i32
For those interested in more details about Pixel Visual Core, the 6th editi...
2018 Jan 17
1
Does it make sense to upstream some MVT's?
...we have added:
>
>
>
> 16x16 element (2D SIMD) 1-bit predicate registers:
>
> v256i1
>
>
>
> 16x16 element (2D SIMD) 16-bit registers:
>
> v256i16
>
>
>
> 20x20 element (2D SIMD) 16-bit registers: (we round up to v512 instead of
> v400):
>
> v512i16
>
>
>
> 32-bit versions of the above 16-bit registers (to represent 32-bit
> accumulators for MAD instructions and also dual-issue "wide" instructions
> to the dual non-MAD ALU's in each lane)
>
> v256i32
>
> v512i32
>
>
>
>
>
> For thos...
2017 Jul 28
2
Addressing TableGen's error "Ran out of lanemask bits" in order to use more than 32 subregisters per register
...t;
>
> On 9/20/2016 12:48 PM, Alex Susu wrote:
>> Hello.
>> I managed to use SIMD units with more than 32 lanes (32
>> subregisters per vector
>> register) in TableGen, llc and opt. For example, I use SIMD
>> instructions with types
>> v128i16 and v512i16.
>>
>> An important questions I have is if it is OK to add the types
>> IIT_V128 = 37, IIT_V256
>> = 38 like I did below:
>> enum IIT_Info {
>> ...
>> IIT_V2 = 9,
>> IIT_V4 = 10,
>> IIT_V8...
2017 Jul 28
0
Addressing TableGen's error "Ran out of lanemask bits" in order to use more than 32 subregisters per register
...ies for these types.
Best regards,
Alex
On 9/20/2016 12:48 PM, Alex Susu wrote:
> Hello.
> I managed to use SIMD units with more than 32 lanes (32 subregisters per vector
> register) in TableGen, llc and opt. For example, I use SIMD instructions with types
> v128i16 and v512i16.
>
> An important questions I have is if it is OK to add the types IIT_V128 = 37, IIT_V256
> = 38 like I did below:
> enum IIT_Info {
> ...
> IIT_V2 = 9,
> IIT_V4 = 10,
> IIT_V8 = 11,
> IIT_V16 = 12,
>...
2016 Sep 18
4
Addressing TableGen's error "Ran out of lanemask bits" in order to use more than 32 subregisters per register
Hello.
I've managed to patch the various files from the back end related to
lanemask - now I have 1024-bit long lanemask.
But now I get the following error when giving make llc:
<<error:unhandled vector type width in intrinsic!>>
This error comes from this file
https://github.com/llvm-mirror/llvm/blob/master/utils/TableGen/IntrinsicEmitter.cpp,
comes from the