search for: v4si

Hi All, If the target supports quad-register R0:R1:R2:R3 (Rn is 32-bit register), is it possible mapping quad-register to v4i32 so that the following example work? typedef int v4si __attribute__ ((vector_size (16))); void foo(v4si i) { v4si j = i; } I don't know how to write CallingConv.td to represent the concept of occupying quad-register R0:R1:R2:R3 once seeing v4i32. Any example that I can refer to? Thanks. Regards, chenwj -- Wei-Ren Chen (陳韋任) Hom...

Hi Anton, I assume that's the same as the online demo's "Show LLVM C++ API code" option (http://llvm.org/demo/)? I've tried that with a structure containing four floating-point components but it also appears to add them individually using extract/insert. Maybe I have to try an array of floats... Thanks, Anton -----Original Message----- From: llvmdev-bounces at

Nicolas, > Thanks for the advise, but I'm actually not trying to compile code from > text. For now I'm just trying to construct the function directly. Think of > it as the vector equivalent of the HowToUseJIT.cpp example. llvm2cpp is your friend then. It's now a separate 'target' in llc. It will generate C++ code, which will construct provided IR. -- With best

...preliminary instructions. At the pointer of custom > lowering register allocation has not yet been done, so I don't have > a way to communicate the dependency. > An example is in order: If I have a register v4r0 with subregisters {r0, r1, r2, r3} and a DAG that looks like load v4si <- extract_element 2 <- add -> load i32 I'd like to be able to generate load v4r0 load r10 add r11, r10, r2 <== subregister 2 of v4r0 -- Christopher Lamb

On Apr 23, 2007, at 12:31 PM, Chris Lattner wrote: > On Mon, 23 Apr 2007, Christopher Lamb wrote: >> How can one let the back end know how to insert and extract >> elements of >> a vector through sub-register copies? I'm at a loss how to do this... > > You probably want to custom lower the insertelement/extractelement > operations for the cases you support.

GCCBuiltin just gives it a name for clang to lookup. Generally they match up with builtins that gcc also implements, but that's not a requirement. If you add a builtin with the same name to the builtin file in clang's include/clang/Basic/Builtins*.def then they will find each other. You can also just add a builtin to clang's builtin file and catch it in clang's

...the scalar > operations don't get optimised very much. The only pass that runs after > type legalisation and still understands the function at an operational > level is DAGCombiner, which is only block-local. > > Take for example something like: > > typedef unsigned int V4SI __attribute__ ((vector_size (16))); > void foo (V4SI *vec, unsigned int n, unsigned int x) > { > V4SI factor = { x, 2, 4, 8 }; > for (unsigned i = 0; i < n; ++i) > vec[i] *= factor; > } > > Without the Scalarizer pass, this multiplication remains a vector &...

I've created an intrinsic from my target, but I can't figure out how I can run it from a C code. Most of the targets have a GCCBuiltin and it looks like it is the way to execute an intrinsic from C code. However in my case there is no actual GCC built in. Any help on this is really appreciated. -- Rail Shafigulin Software Engineer Esencia Technologies -------------- next part

...>> custom lowering register allocation has not yet been done, so I >> don't have a way to communicate the dependency. >> > > An example is in order: > > If I have a register v4r0 with subregisters {r0, r1, r2, r3} and a > DAG that looks like > > load v4si <- extract_element 2 <- add -> load i32 > > I'd like to be able to generate > > load v4r0 > load r10 > add r11, r10, r2 <== subregister 2 of v4r0 I see that Evan has added getSubRegisters()/getSuperRegisters() to MRegisterInfo. This is what's needed in order...

...ions. At the pointer of >>> custom lowering register allocation has not yet been done, so I >>> don't have a way to communicate the dependency. Ok. >> If I have a register v4r0 with subregisters {r0, r1, r2, r3} and a >> DAG that looks like >> >> load v4si <- extract_element 2 <- add -> load i32 >> >> I'd like to be able to generate >> >> load v4r0 >> load r10 >> add r11, r10, r2 <== subregister 2 of v4r0 Nice ISA. That is entirely too logical. :) We have a similar problem on X86. In particular,...