Displaying 6 results from an estimated 6 matches for "v4sf".
2012 Nov 28
0
[LLVMdev] [llvm-commits] [dragonegg] r168787 - in /dragonegg/trunk: src/x86/Target.cpp src/x86/x86_builtins test/validator/c/copysignp.c
...==============================================================
> --- dragonegg/trunk/test/validator/c/copysignp.c (added)
> +++ dragonegg/trunk/test/validator/c/copysignp.c Wed Nov 28 06:44:50 2012
> @@ -0,0 +1,7 @@
> +// RUN: %dragonegg -S %s
> +// PR12664
> +
> +typedef float v4sf __attribute__ ((vector_size (16)));
> +v4sf foo(v4sf l, v4sf r) {
> + return __builtin_ia32_copysignps (l, r);
> +}
>
>
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2019 Sep 27
2
Opportunity to split store of shuffled vector.
...vide a buildable example?
Sorry, I should provide a cross-platform version using vector
extension of frontend :) `vector int` is a vector extension on
PowerPC, which is enabled if you set target to PowerPC platforms.
Example below should be successfully compiled in any platform:
typedef float v4sf __attribute__ ((vector_size(16)));
void foo(v4sf *a) {
(*a)[0] = 1;
(*a)[3] = 2;
}
And we can get the IR mentioned before:
%0 = load <4 x float>, <4 x float>* %a, align 16
%vecins1 = shufflevector <4 x float> <float 1.000000e+00, float
undef, floa...
2017 Jul 20
2
[RFC] dereferenceable metadata
Indeed. But the problem here is that Dinar is trying to keep information
after a load/store is removed by instcombine
For example:
v4sf v = {p[0], p[1], p[2], p[3]};
v4sf v2 = shuffle(v, 0, 0, 2, 2);
Some pass comes in and removes the p[3] and p[1].
Now you have smaller code, but lost the ability to use a vector load for
all those values + shuffle. The code got scalarized because we lost the
information that p[3] is valid.
The a...
2019 Oct 04
2
Opportunity to split store of shuffled vector.
...rovide a cross-platform version using vector
>> extension of frontend :) `vector int` is a vector extension on
>> PowerPC, which is enabled if you set target to PowerPC platforms.
>> Example below should be successfully compiled in any platform:
>>
>> typedef float v4sf __attribute__ ((vector_size(16)));
>>
>> void foo(v4sf *a) {
>> (*a)[0] = 1;
>> (*a)[3] = 2;
>> }
>>
>> And we can get the IR mentioned before:
>>
>> %0 = load <4 x float>, <4 x float>* %a, align 16
>>...
2019 Sep 26
2
Opportunity to split store of shuffled vector.
Hi there,
I notice that LLVM seems to always generate vector instructions for
vector operations in C, even it's just simple stores:
void foo(vector int* c) {
(*c)[0] = 1;
(*c)[1] = 2;
}
%0 = load <4 x i32>, <4 x i32>* %c, align 16
%vecins1 = shufflevector <4 x i32> <i32 1, i32 2, i32 undef, i32
undef>, <4 x i32> %0, <4 x i32> <i32 0, i32 1, i32 6,
2017 Jul 18
2
[RFC] dereferenceable metadata
Hi,
While working on PR21780, I used "dereferenceable_or_null" metadata
and I realized now that it is not correct for my solution to use this
metadata type since it might point to an address that it is not
dereferenceable but null. I think that we need another new metadata
type, something like "dereferenceable" with that we could annotate
any load (not just pointer type like