search for: v4r0

...beginning to add vector registers to a back end I came across the following problem: as soon as I define two sets of registers that have a many-to-one mapping the live interval pass appears to double- kill the mapped-onto register. I have the following excerpts from my RegisterInfo.td. def V4R0 : R4v<0 , "V4R0 ", []>, DwarfRegNum<0>; def R0 : Rg<0 , "R0", [V4R0]>, DwarfRegNum<0>; def R1 : Rg<1 , "R1", [V4R0]>, DwarfRegNum<1>; when trying to compile: define void @_Z3fooii(i32 %a, i32 %b) { entry: %retval =...

...sters to a back end I came across > the following problem: as soon as I define two sets of registers > that have a many-to-one mapping the live interval pass appears to > double-kill the mapped-onto register. I have the following excerpts > from my RegisterInfo.td. > > def V4R0 : R4v<0 , "V4R0 ", []>, DwarfRegNum<0>; > > def R0 : Rg<0 , "R0", [V4R0]>, DwarfRegNum<0>; > def R1 : Rg<1 , "R1", [V4R0]>, DwarfRegNum<1>; How are R4v and Rg defined? > > when trying to compile: > > defi...

...me >> across the following problem: as soon as I define two sets of >> registers that have a many-to-one mapping the live interval pass >> appears to double-kill the mapped-onto register. I have the >> following excerpts from my RegisterInfo.td. >> >> def V4R0 : R4v<0 , "V4R0 ", []>, DwarfRegNum<0>; >> >> def R0 : Rg<0 , "R0", [V4R0]>, DwarfRegNum<0>; >> def R1 : Rg<1 , "R1", [V4R0]>, DwarfRegNum<1>; > > How are R4v and Rg defined? class Rg<bits<6> n...

On Apr 3, 2007, at 3:45 PM, Christopher Lamb wrote: > >> Can you dump out the machine basic block? It should have an >> implicit use of V4R0 at first ORI but it should not be marked kill. >> If it is marked kill, then you need to walk LiveVariables.cpp to >> find out why. > > Here is the beginning of the BB dump. > > entry (0x8503c80, LLVM BB @0x8501af0, ID#0): > Live Ins: %R0 %R1 > %reg1024 = ORI %R0<k...

...it's simply based on using subregister operands in > subsequent/preliminary instructions. At the pointer of custom > lowering register allocation has not yet been done, so I don't have > a way to communicate the dependency. > An example is in order: If I have a register v4r0 with subregisters {r0, r1, r2, r3} and a DAG that looks like load v4si <- extract_element 2 <- add -> load i32 I'd like to be able to generate load v4r0 load r10 add r11, r10, r2 <== subregister 2 of v4r0 -- Christopher Lamb

On Apr 23, 2007, at 12:31 PM, Chris Lattner wrote: > On Mon, 23 Apr 2007, Christopher Lamb wrote: >> How can one let the back end know how to insert and extract >> elements of >> a vector through sub-register copies? I'm at a loss how to do this... > > You probably want to custom lower the insertelement/extractelement > operations for the cases you support.

...bregister >> operands in subsequent/preliminary instructions. At the pointer of >> custom lowering register allocation has not yet been done, so I >> don't have a way to communicate the dependency. >> > > An example is in order: > > If I have a register v4r0 with subregisters {r0, r1, r2, r3} and a > DAG that looks like > > load v4si <- extract_element 2 <- add -> load i32 > > I'd like to be able to generate > > load v4r0 > load r10 > add r11, r10, r2 <== subregister 2 of v4r0 I see that Evan has added getS...

...t's simply based on using subregister >>> operands in subsequent/preliminary instructions. At the pointer of >>> custom lowering register allocation has not yet been done, so I >>> don't have a way to communicate the dependency. Ok. >> If I have a register v4r0 with subregisters {r0, r1, r2, r3} and a >> DAG that looks like >> >> load v4si <- extract_element 2 <- add -> load i32 >> >> I'd like to be able to generate >> >> load v4r0 >> load r10 >> add r11, r10, r2 <== subregister 2 of v4...