search for: v4f16

Displaying 5 results from an estimated 5 matches for "v4f16".

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2017 Jan 23
2
Changes to TableGen in v4.0?
...und, merging 'v2f32' into 'v2f16' For the scalar version, the conflict is between two rules that have different mutually exclusive predicates (for alternative chip versions). But in the case of the vector, the conflict is for a vector of a different size, in the case: [(set (v4f16 VF16:$dst), (fround (v4f32 VF32:$src)))] and 'CONV_v4f32_v4f16'. What adjustments do I need to make to the TD descriptions to make these work again? I know that FP16 is not hugely common on the mainstream platforms, but it is vital to ours. I did notice that 'fextend' was...
2019 Jul 12
2
[cfe-dev] ARM float16 intrinsic test
...; } I tried: $$COMP_ROOT/clang -cc1 -triple thumbv7s-apple-darwin -target-abi apcs-gnu -target-cpu swift -fallow-half-arguments-and-returns -target-feature +fullfp16 -ffreestanding -disable-O0-optnone -emit-llvm -o arm.ll arm.cpp $cat arm.ll | grep llvm.arm call void @llvm.arm.neon.vst4lane.p0i8.v4f16(i8* %4, <4 x half> %13, <4 x half> %14, <4 x half> %15, <4 x half> %16, i32 3, i32 2) declare void @llvm.arm.neon.vst4lane.p0i8.v4f16(i8*, <4 x half>, <4 x half>, <4 x half>, <4 x half>, i32, i32) #1 $$COMP_ROOT/llc arm.ll unhandled vld/vst lane type...
2020 Jun 30
5
[RFC] Semi-Automatic clang-format of files with low frequency
I 100% get that we might not like the decisions clang-format is making, but how does one overcome this when adding new code? The pre-merge checks enforce clang-formatting before commit and that's a common review comment anyway for those who didn't join the pre-merge checking group. I'm just wondering are we not all following the same guidelines? Concerns of clang-format not being good
2018 Apr 09
2
A way to opt out of a dag combine?
...ave any target specific hooks. Exhaustive testing of x86-64 vector code doesn't show the error. I think the other in tree targets would notice the vector transform getting the answer wrong (it's harder to confirm without hardware), so the bug is probably inert for in tree targets. Given a v4f16 instance t2, the DAG describes building a v2f16 vector from elements [0, 2]. The combine translates this to building a vector from elements [0, 0]. The problem seems to be treating extract_subvector with different constants as instances of the same value. t14: v2f16 = extract_subvector t2, Consta...
2017 Sep 10
2
Question about quad-register
Hi All, If the target supports quad-register R0:R1:R2:R3 (Rn is 32-bit register), is it possible mapping quad-register to v4i32 so that the following example work? typedef int v4si __attribute__ ((vector_size (16))); void foo(v4si i) { v4si j = i; } I don't know how to write CallingConv.td to represent the concept of occupying quad-register R0:R1:R2:R3 once seeing