Displaying 7 results from an estimated 7 matches for "v32i64".
Did you mean:
v2i64
2018 Apr 10
1
64 bit mask in x86vshuffle instruction
...equisite ISA extensions for that element type are available.
switch (VT.SimpleTy) {
case MVT::v32f64:
return lowerV32F64VectorShuffle(DL, Mask, Zeroable, V1, V2, Subtarget,
DAG);
case MVT::v64f32:
return lowerV64F32VectorShuffle(DL, Mask, Zeroable, V1, V2, Subtarget,
DAG);
case MVT::v32i64:
return lowerV32I64VectorShuffle(DL, Mask, Zeroable, V1, V2, Subtarget,
DAG);
case MVT::v64i32:
return lowerV64I32VectorShuffle(DL, Mask, Zeroable, V1, V2, Subtarget,
DAG);
default:
llvm_unreachable("Not a valid P x86 vector type!");
}
}
static SDValue lowerV64I32Vecto...
2017 Jul 11
2
Using new types v32f32, v32f64 in llvm backend not possible
Hello,
i want to work with these types v32f32, v32f64.... in llvm which are
undefined in the backend?
But v32i32, v32i64 are already defined so i am able to use these.
but for other types such as v32f32, v32f64 although i have defined them
appropriately in all the files like machinevaluetype.h, valuetypes.cpp
etc. i have checked it many times but still getting the following error
when build in debug mode.
llvm-tbl...
2017 Jul 11
2
Using new types v32f32, v32f64 in llvm backend not possible
...On Tue, Jul 11, 2017 at 6:20 PM, Hal Finkel <hfinkel at anl.gov> wrote:
>
> On 07/11/2017 03:22 AM, hameeza ahmed wrote:
>
>> Hello,
>>
>> i want to work with these types v32f32, v32f64.... in llvm which are
>> undefined in the backend?
>> But v32i32, v32i64 are already defined so i am able to use these.
>>
>> but for other types such as v32f32, v32f64 although i have defined them
>> appropriately in all the files like machinevaluetype.h, valuetypes.cpp
>> etc. i have checked it many times but still getting the following error...
2017 Jul 12
2
Using new types v32f32, v32f64 in llvm backend not possible
...wrote:
>>
>>>
>>> On 07/11/2017 03:22 AM, hameeza ahmed wrote:
>>>
>>>> Hello,
>>>>
>>>> i want to work with these types v32f32, v32f64.... in llvm which are
>>>> undefined in the backend?
>>>> But v32i32, v32i64 are already defined so i am able to use these.
>>>>
>>>> but for other types such as v32f32, v32f64 although i have defined them
>>>> appropriately in all the files like machinevaluetype.h, valuetypes.cpp
>>>> etc. i have checked it many times but st...
2016 Dec 12
0
TableGen - Help to implement a form of gather/scatter operations for Mips MSA
...Split node result: t123: v64i64 = BUILD_VECTOR undef:i64, undef:i64, undef:i64,
undef:i64, undef:i64, undef:i64, undef:i64, undef:i64, undef:i64, undef:i64, undef:i64,
undef:i64, undef:i64, undef:i64, undef:i64, undef:i64, undef:i64, undef:i64, undef:i64,
undef:...
Split node result: t124: v32i64 = BUILD_VECTOR undef:i64, undef:i64, undef:i64,
undef:i64, undef:i64, undef:i64, undef:i64, undef:i64, undef:i64, undef:i64, undef:i64,
undef:i64, undef:i64, undef:i64, undef:i64, undef:i64, undef:i64, undef:i64, undef:i64,
undef:...
Split node result: t125: v16i64 = BUILD_VECTOR undef:i64,...
2016 Dec 15
2
TableGen - Help to implement a form of gather/scatter operations for Mips MSA
...lt: t123: v64i64 = BUILD_VECTOR undef:i64, undef:i64, undef:i64,
> undef:i64, undef:i64, undef:i64, undef:i64, undef:i64, undef:i64, undef:i64, undef:i64,
> undef:i64, undef:i64, undef:i64, undef:i64, undef:i64, undef:i64, undef:i64, undef:i64,
> undef:...
> Split node result: t124: v32i64 = BUILD_VECTOR undef:i64, undef:i64, undef:i64,
> undef:i64, undef:i64, undef:i64, undef:i64, undef:i64, undef:i64, undef:i64, undef:i64,
> undef:i64, undef:i64, undef:i64, undef:i64, undef:i64, undef:i64, undef:i64, undef:i64,
> undef:...
> Split node result: t125: v16i64 = BUILD_V...
2016 Dec 11
2
TableGen - Help to implement a form of gather/scatter operations for Mips MSA
Hello.
Will, thanks a lot for pointing me to the MaskedGatherSDNode and mgatherv4i32. I have
to say that the definition of the "multiclass avx512_gather" from
lib/Target/X86/X86InstrAVX512.td is difficult to follow and I prefer not to use it.
I currently have some serious problems with TableGen - it gives an assertion failure: