search for: v32i1

Hello, Context: We have a backend where v32i1 is a Legal type, but the storage for v32i1 is not 32-bits/uses a different instruction sequence. We ran into an issue because combineLoadToOperationType changed v32i1 loads into i32 loads, so a sequence like: define void @bits(<32 x i1>* %A, <32 x i1>* %B) { %a = load <32 x i1>,...

...or us is code generation support for the Haswell new instructions pext and pdep. These instructions shuffle bits within a 64-bit word, either gathering all selected bits to the beginning (pext) or scattering some initial bits throughout (pdep). A natural model for this is to use shufflevector on v32i1 and v64i1 vectors. We've got some preliminary notes here: http://parabix.costar.sfu.ca/wiki/BitShuffle Since we're quite new at this, I have some questions about strategy. (1) First, it seems that legalizing v32i1 and v64i1 types for x86 would make sense. This will allow us to retain...