Displaying 4 results from an estimated 4 matches for "v32f64".
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2017 Jul 11
2
Using new types v32f32, v32f64 in llvm backend not possible
Hello,
i want to work with these types v32f32, v32f64.... in llvm which are
undefined in the backend?
But v32i32, v32i64 are already defined so i am able to use these.
but for other types such as v32f32, v32f64 although i have defined them
appropriately in all the files like machinevaluetype.h, valuetypes.cpp
etc. i have checked it many times but st...
2017 Jul 11
2
Using new types v32f32, v32f64 in llvm backend not possible
...to accomplish this???
I am really stuck at this point.
Please guide me.
Thank You
On Tue, Jul 11, 2017 at 6:20 PM, Hal Finkel <hfinkel at anl.gov> wrote:
>
> On 07/11/2017 03:22 AM, hameeza ahmed wrote:
>
>> Hello,
>>
>> i want to work with these types v32f32, v32f64.... in llvm which are
>> undefined in the backend?
>> But v32i32, v32i64 are already defined so i am able to use these.
>>
>> but for other types such as v32f32, v32f64 although i have defined them
>> appropriately in all the files like machinevaluetype.h, valuetypes....
2017 Jul 12
2
Using new types v32f32, v32f64 in llvm backend not possible
...You
>>
>>
>> On Tue, Jul 11, 2017 at 6:20 PM, Hal Finkel <hfinkel at anl.gov> wrote:
>>
>>>
>>> On 07/11/2017 03:22 AM, hameeza ahmed wrote:
>>>
>>>> Hello,
>>>>
>>>> i want to work with these types v32f32, v32f64.... in llvm which are
>>>> undefined in the backend?
>>>> But v32i32, v32i64 are already defined so i am able to use these.
>>>>
>>>> but for other types such as v32f32, v32f64 although i have defined them
>>>> appropriately in all the fil...
2018 Apr 10
1
64 bit mask in x86vshuffle instruction
.... If we don't have support
for
// specific element type shuffles at 512 bits, immediately split them and
// lower them. Each lowering routine of a given type is allowed to assume
that
// the requisite ISA extensions for that element type are available.
switch (VT.SimpleTy) {
case MVT::v32f64:
return lowerV32F64VectorShuffle(DL, Mask, Zeroable, V1, V2, Subtarget,
DAG);
case MVT::v64f32:
return lowerV64F32VectorShuffle(DL, Mask, Zeroable, V1, V2, Subtarget,
DAG);
case MVT::v32i64:
return lowerV32I64VectorShuffle(DL, Mask, Zeroable, V1, V2, Subtarget,
DAG);
case MVT::v64...