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v2f32regsregisterclass
2012 Mar 02
1
[LLVMdev] vector shuffle emulation/expand in backend?
I'm having some troubles implementing vector support to our custom backend
It seems that llvm cannot emulate shuffle with extracts, inserts and builds?
I've enabled vector registers with
addRegisterClass(MVT::v2i32, TCE::V2I32RegsRegisterClass);
addRegisterClass(MVT::v2f32, TCE::V2F32RegsRegisterClass);
and created patterns for most vector instructions, including insert,
extract and build.
I've tried to say
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Expand);
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f32, Expand);
b...