search for: v2048i32

...y the ********my backend supports v64i32 i mean my hardware. > > On Wed, Jul 12, 2017 at 12:49 AM, hameeza ahmed <hahmed2305 at gmail.com> > wrote: > >> Thank you so much. it run fine. >> Can you please resolve following issue; >> >> I now have support for v2048i32 >> but my backend supports v64i32 >> so ultimately v2048i32 needs to be split into 32 v64i32 instructions. the >> only difference between 2 is if its orginally v2048i32 i want my registers >> assignment from REG_A set. if its v64i32 originally, then i want registers >>...

Thank you so much. it run fine. Can you please resolve following issue; I now have support for v2048i32 but my backend supports v64i32 so ultimately v2048i32 needs to be split into 32 v64i32 instructions. the only difference between 2 is if its orginally v2048i32 i want my registers assignment from REG_A set. if its v64i32 originally, then i want registers from set REG_B. How to accomplish this???...

...s vector width since i have used v64i32 in my backend. now if vector width=64. i want the Reg_B class registers to be assigned and if vector width=2048 i want Reg_A registers to be assigned to instruction. Should i incorporate the solution in lowering stage? some thing like; addRegisterClass(MVT::v2048i32, &X86::Reg_B); setOperationAction(ISD::MNLOAD, MVT::v2048i32, custom); then in function LowerOperation(SDValue Op, SelectionDAG &DAG) i should do, case ISD::MNLOAD: return LOAD2048(Op, Subtarget, DAG); then i will implement static SDValue LOA...

Hello, i want to work with these types v32f32, v32f64.... in llvm which are undefined in the backend? But v32i32, v32i64 are already defined so i am able to use these. but for other types such as v32f32, v32f64 although i have defined them appropriately in all the files like machinevaluetype.h, valuetypes.cpp etc. i have checked it many times but still getting the following error when build in

...f iterations=15 we see 1<8xi32> and rest scalar. so here when i keep iteration=2047 i get all scalar why is that so? similarly in polly as well i cant see vector mixes like its happening for KNL it emits <v16i32>, <v8i32>,<v4i32>...so here it should emit recursively like <v2048i32> <v1024i32> <v512i32>.....<v32i32> how to do this? What am i missing here? what further changes do i need to make? Please help... On Tue, Jul 24, 2018 at 1:52 AM, Friedman, Eli <efriedma at codeaurora.org> wrote: > On 7/23/2018 12:40 PM, hameeza ahmed wrote:...

...;8xi32> and rest scalar. so here when i keep iteration=2047 i get all >> scalar why is that so? similarly in polly as well i cant see vector mixes >> like its happening for KNL it emits <v16i32>, <v8i32>,<v4i32>...so here it >> should emit recursively like <v2048i32> <v1024i32> <v512i32>.....<v32i32> >> >> how to do this? >> >> What am i missing here? >> what further changes do i need to make? >> >> Please help... >> >> >> >> >> >> >> On Tue, Jul 24, 2018 a...

hello, i have a situation where i have to assign the registers to instructions based on the loop iterations. for eg.. the registers are: R_0_V_0, R_0_V_1, R_0_V_2, R_0_V_3, R_1_V_0, R_1_V_1, R_1_V_2, R_1_V_3, R_2_V_0, R_2_V_1, R_2_V_2, R_2_V_3. These registers defined in object Reg_A These are total 12 registers. will use them contiguously, here i define it in above mentioned order i.e

Thank You. I got it. Version issue. TTI.getRegisterBitWidth(true) How to put my target machine info in TTI? Please help. On Mon, Jul 23, 2018 at 11:33 PM, Friedman, Eli <efriedma at codeaurora.org> wrote: > On 7/23/2018 10:49 AM, hameeza ahmed via llvm-dev wrote: > > Thank You. > > But I cannot find your mentioned function