Displaying 6 results from an estimated 6 matches for "v16i64".
2020 Jun 30
5
[RFC] Semi-Automatic clang-format of files with low frequency
I 100% get that we might not like the decisions clang-format is making, but
how does one overcome this when adding new code? The pre-merge checks
enforce clang-formatting before commit and that's a common review comment
anyway for those who didn't join the pre-merge checking group. I'm just
wondering are we not all following the same guidelines?
Concerns of clang-format not being good
2015 Mar 15
2
[LLVMdev] Indexed Load and Store Intrinsics - proposal
...t;16 x float> @llvm.sindex.load.v16f32.v16i32 (i8 *%ptr, <16 x i32> %index,
> i32 %scale)
> <16 x float> @llvm.masked.sindex.load.v16f32.v16i32 (i8 *%ptr, <16 x i32>
> %index, <16 x float> %passthru, <16 x i1> %mask)
> void @llvm.sindex.store.v16f32.v16i64(i8* %ptr, <16 x float> %value, <16 x
> 164> %index, i32 %scale, <16 x i1> %mask)
>
> Comments?
>
> Thank you.
>
>
> Elena
>
>
>
>
>
> ---------------------------------------------------------------------
> Intel Israel (74) Limited
&...
2014 Dec 18
8
[LLVMdev] Indexed Load and Store Intrinsics - proposal
...tore.
Examples:
<16 x float> @llvm.sindex.load.v16f32.v16i32 (i8 *%ptr, <16 x i32> %index, i32 %scale)
<16 x float> @llvm.masked.sindex.load.v16f32.v16i32 (i8 *%ptr, <16 x i32> %index, <16 x float> %passthru, <16 x i1> %mask)
void @llvm.sindex.store.v16f32.v16i64(i8* %ptr, <16 x float> %value, <16 x 164> %index, i32 %scale, <16 x i1> %mask)
Comments?
Thank you.
- Elena
---------------------------------------------------------------------
Intel Israel (74) Limited
This e-mail and any attachments may contain confidential mat...
2016 Dec 12
0
TableGen - Help to implement a form of gather/scatter operations for Mips MSA
...Split node result: t124: v32i64 = BUILD_VECTOR undef:i64, undef:i64, undef:i64,
undef:i64, undef:i64, undef:i64, undef:i64, undef:i64, undef:i64, undef:i64, undef:i64,
undef:i64, undef:i64, undef:i64, undef:i64, undef:i64, undef:i64, undef:i64, undef:i64,
undef:...
Split node result: t125: v16i64 = BUILD_VECTOR undef:i64, undef:i64, undef:i64,
undef:i64, undef:i64, undef:i64, undef:i64, undef:i64, undef:i64, undef:i64, undef:i64,
undef:i64, undef:i64, undef:i64, undef:i64, undef:i64...
Split node result: t126: v8i64 = BUILD_VECTOR undef:i64, undef:i64, undef:i64,
undef:i64, undef:i6...
2016 Dec 15
2
TableGen - Help to implement a form of gather/scatter operations for Mips MSA
...lt: t124: v32i64 = BUILD_VECTOR undef:i64, undef:i64, undef:i64,
> undef:i64, undef:i64, undef:i64, undef:i64, undef:i64, undef:i64, undef:i64, undef:i64,
> undef:i64, undef:i64, undef:i64, undef:i64, undef:i64, undef:i64, undef:i64, undef:i64,
> undef:...
> Split node result: t125: v16i64 = BUILD_VECTOR undef:i64, undef:i64, undef:i64,
> undef:i64, undef:i64, undef:i64, undef:i64, undef:i64, undef:i64, undef:i64, undef:i64,
> undef:i64, undef:i64, undef:i64, undef:i64, undef:i64...
> Split node result: t126: v8i64 = BUILD_VECTOR undef:i64, undef:i64, undef:i64,
> und...
2016 Dec 11
2
TableGen - Help to implement a form of gather/scatter operations for Mips MSA
Hello.
Will, thanks a lot for pointing me to the MaskedGatherSDNode and mgatherv4i32. I have
to say that the definition of the "multiclass avx512_gather" from
lib/Target/X86/X86InstrAVX512.td is difficult to follow and I prefer not to use it.
I currently have some serious problems with TableGen - it gives an assertion failure: