search for: v16i1

When LLVM does a comparison of two vectors, in this case with 16 elements, the returned type of setcc is v16i1. The architecture I'm targeting allows storing the result of a vector comparison as a bit mask in a scalar register, but I'm having trouble converting the result of setcc into a value that is usable there. For example, if I try to AND together masks that are the results of two comparisons,...

...custom instruction set that supports predication for all vector operations, but uses general purpose scalar registers to store predicate values (vector comparisons results are also stored as a bit mask in a scalar register). I've currently specified that scalar registers can be either of type v16i1 (for predicates; vectors have 16 elements) or i32, which would allow them to work in either context: def ScalarReg : RegisterClass<"VP", [i32, v16i1… I soon realized this has an onerous side effect. Since vector comparison results (of type v16i1) can be used in arithmetic, most inst...

Hal, thank you for your opinion. I just was confused when I saw so long name " llvm.masked.load.v16i32.p0i32.v16i32.i32.v16i1" . If we stay with a short name, we do a step towards instruction form. - Elena -----Original Message----- From: Hal Finkel [mailto:hfinkel at anl.gov] Sent: Sunday, October 26, 2014 17:06 To: Demikhovsky, Elena Cc: llvmdev at cs.uiuc.edu Subject: Re: [LLVMdev] Masked vector intrinsics...

Hi, The proposed masked vector intrinsics are overloaded - one intrinsic ID for multiple types. After name mangling it will look like: %res = call <16 x i32> @llvm.masked.load.v16i32.p0i32.v16i32.i32.v16i1(i32* %addr, <16 x i32>%passthru, i32 4, <16 x i1> %mask) 6 types x 3 vector sizes = 18 names for one operation I propose to remove name mangling from these intrinsics: %res = call <16 x i32> @llvm.masked.load (i32* %addr, <16 x i32>%passthru, i32 4, <16 x i1> %mask)...

...dst = $oldvalue" in { > def MASKEDARITH : MyInstruction< > (outs VectorReg:$dst), > (ins MaskReg:$mask, VectorReg:$src1, VectorReg:$src2, > VectorReg:$oldvalue), > "add $dst {$mask}, $src1, $src2", > [(set v16i32:$dst, (vselect v16i1:$mask, (add v16i32:$src1, > v16i32:$src2), v16i32:$oldvalue))]>; > } Ok, but where does $oldvalue come from? That is the trickty part as far as I can see and is why this isn't quite the same as handling two-address instructions. I agree that the pattern itself is straightforward. I...

...s.uiuc.edu >> Sent: Sunday, October 26, 2014 10:17:49 AM >> Subject: RE: [LLVMdev] Masked vector intrinsics and name mangling >> >> Hal, thank you for your opinion. >> I just was confused when I saw so long name " >> llvm.masked.load.v16i32.p0i32.v16i32.i32.v16i1" . >> If we stay with a short name, we do a step towards instruction form. > > I completely understand, I just don't think it matters all that much, and the logic necessary to handle it will just become a source of bugs (and thus a distraction). You don't need to worry abo...

Hey guys, There seems to be an inconsistency between mask operand types for the AVX512 intrinsics. The mask instruction intrinsics expect a v16i1 for the mask operands: > def int_x86_kadd_v16i1 : GCCBuiltin<"__builtin_ia32_kaddw">, > Intrinsic<[llvm_v16i1_ty], [llvm_v16i1_ty, llvm_v16i1_ty], > [IntrNoMem]>; But other intrinsics expect a i8/i16 as the mask operand: > d...

...{ >> def MASKEDARITH : MyInstruction< >> (outs VectorReg:$dst), >> (ins MaskReg:$mask, VectorReg:$src1, VectorReg:$src2, >> VectorReg:$oldvalue), >> "add $dst {$mask}, $src1, $src2", >> [(set v16i32:$dst, (vselect v16i1:$mask, (add v16i32:$src1, >> v16i32:$src2), v16i32:$oldvalue))]>; >> } > > Ok, but where does $oldvalue come from? That is the trickty part as far > as I can see and is why this isn't quite the same as handling > two-address instructions. I may be missing some impor...

...s): let Constraints = "$dst = $oldvalue" in { def MASKEDARITH : MyInstruction< (outs VectorReg:$dst), (ins MaskReg:$mask, VectorReg:$src1, VectorReg:$src2, VectorReg:$oldvalue), "add $dst {$mask}, $src1, $src2", [(set v16i32:$dst, (vselect v16i1:$mask, (add v16i32:$src1, v16i32:$src2), v16i32:$oldvalue))]>; } That's actually pretty clean. Thanks On Thu, May 9, 2013 at 2:15 PM, Arnold Schwaighofer <aschwaighofer at apple.com> wrote: > > On May 9, 2013, at 3:05 PM, Jeff Bush <jeffbush001 at gmail.com> wrote: >...

On May 9, 2013, at 3:05 PM, Jeff Bush <jeffbush001 at gmail.com> wrote: > On Thu, May 9, 2013 at 8:10 AM, <dag at cray.com> wrote: >> Jeff Bush <jeffbush001 at gmail.com> writes: >> >>> %tx = select %mask, %x, <0.0, 0.0, 0.0 ...> >>> %ty = select %mask, %y, <0.0, 0.0, 0.0 ...> >>> %sum = fadd %tx, %ty >>> %newvalue

...t; in { >> def MASKEDARITH : MyInstruction< >> (outs VectorReg:$dst), >> (ins MaskReg:$mask, VectorReg:$src1, VectorReg:$src2, >> VectorReg:$oldvalue), >> "add $dst {$mask}, $src1, $src2", >> [(set v16i32:$dst, (vselect v16i1:$mask, (add v16i32:$src1, >> v16i32:$src2), v16i32:$oldvalue))]>; >> } > > Ok, but where does $oldvalue come from? That is the trickty part as far > as I can see and is why this isn't quite the same as handling > two-address instructions. >From the semantics of...

...::SETCC Constant:i8<4>, t21 t23: i32 = zero_extend t22 t14: ch,glue = CopyToReg t0, Register:i32 %EAX, t23 t24: i16,ch = load<LD1[%XXX](align=4)(dereferenceable), zext from i8> t0, FrameIndex:i64<0>, undef:i64 t26: i16 = AssertZext t24, ValueType:ch:i4 t19: v16i1 = bitcast t26 t15: ch = X86ISD::RET_FLAG t14, TargetConstant:i32<0>, Register:i32 %EAX, t14:1 -Eli -- Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project

Hello, I'm working on support for the SIMD instruction set on our new BG/Q supercomputer. This instruction set is v4f64 (with the exception of some int <-> fp conversions, floating-point only). The vectorized comparisons, logical operations and selects also exclusively use floating-point inputs. For those inputs that are logically vectors of booleans the system uses the following

On Thu, Oct 20, 2016 at 12:05 PM, Mehdi Amini <mehdi.amini at apple.com> wrote: > >> On Oct 20, 2016, at 8:54 AM, Cameron McInally via llvm-dev <llvm-dev at lists.llvm.org> wrote: >> >> Hey guys, >> >> I've hit a pretty nasty issue on SKX with ANDs of masks <= 4 bits. >> >> In the IR, we represent a 4b vector mask as <4 x i1>.