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2020 Jul 08
4
[RFC] Saturating left shift intrinsics
Hello,
This is an RFC for adding intrinsics which perform saturating signed/unsigned left shift.
There is currently a patch on Phabricator here:
https://reviews.llvm.org/D83216
The intrinsics are of the form
i32 @llvm.sshl.sat.i32(i32, i32)
i32 @llvm.ushl.sat.i32(i32, i32)
<4 x i32> @llvm.sshl.sat.v4i32(<4 x i32>, <4 x i32>)
<4 x i32> @llvm.ushl.sat.v4i32(<4 x i32>, <4 x i32>)
and are overloaded with a single type which can be either an integer type or a vector of integers. The value(s) provided in the fi...