search for: usescustominserter

...32imm:$amt1, i32imm:$amt2), [(MyCallseqEnd timm:$amt1, timm:$amt2)]>; } def Custom_CALL : Pseudo<(outs), (ins IRF32:$target, variable_ops), [(my_call IRF32:$target)]> { let isCall = 1; let usesCustomInserter = 1; } def Custom_RETURN : Pseudo<(outs), (ins variable_ops), [(my_ret)]> { let isReturn = 1; let usesCustomInserter = 1; } but when I compile the following C code: int foo(int); int bar() { return foo(42); } it crashes with...

...rgetConstant and passed it as MachineOperand to the MachineInstruction? Opcode definition (Target/Target.td) ============== +def PATCHABLE_LOG_CALL : Instruction { + let OutOperandList = (outs); + let InOperandList = (ins unknown:$entry); + let AsmString = "# XRay Custom Log."; + let usesCustomInserter = 1; + let hasSideEffects = 1; +} Example IR for the graph above =========== define i32 @caller() nounwind noinline uwtable "function-instrument"="xray-always" { %logentryptr = alloca i8 call void @llvm.xray.customlog(i8* %logentryptr) ret i32 0 } declare void @ll...

See X86InstrInfo.td let usesCustomInserter = 1, isTwoAddress = 0, Defs = [EFLAGS] in def CMOV_GR8 : I<0, Pseudo, This creates a CMOV_GR8 pseudo instruction at isel time which can be expanded during scheduling time. Evan On Dec 10, 2009, at 11:46 AM, Javier Martinez wrote: > Hello, > > My expansion for an operation uses if a...

...= "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_mpx_bndmk: Intrinsic<[llvm_x86bnd_ty], [llvm_ptr_ty, llvm_i64_ty], []>; } ``` And following instruction that is generated when @llvm.x86.mpx.bndmk is used in code: ``` let isPseudo = 1 in let usesCustomInserter = 1 in def BNDMK64rm_Int: PseudoI<(outs BNDR:$dst), (ins i64mem:$src, GR64:$shift), [(set BNDR:$dst, (int_x86_mpx_bndmk addr:$src, i64:$shift))]>; ``` Everything works completely fine, intrinsic gets matched. But if I add "IntrNoMem" attribute to instrinsic like: ``` let Targe...

Hello, My expansion for an operation uses if and loops. How do I introduce branches in the target lowering stage? Do I have to create basic blocks, add the instructions to them and and add them to the machine function's basic block list? Thanks, Javier

...rking with MachineInst? First, I have defined an instrinsic in "Intrinsics.td": _def int_antivm : Intrinsic<[llvm_i1_ty], [], [], "llvm.antivm">;_ Then I want to lower it in the X86 backend, so I defined a pseudo instruction in "X86InstrCompiler.td": _let usesCustomInserter = 1, Defs = [EFLAGS] in {_ _def ANTIVM : PseudoI<(outs), (ins), [(int_antivm)]>;_ _}_ I wrote my custom inserter: _MachineBasicBlock *_ _X86TargetLowering::EmitANTIVMWithCustomInserter(_ _ MachineInstr *MI,_ _ MachineBasicBlock *MBB) const {_ _ // Some stuff, _ _ MI->eraseFromParent(...

Hello, We have the architecture without conditional moves. Which way can we lower select? As we know there was the special pass a long time ago, but it was deleted. commit c3591a0d48ce045bbf5ae0d78a41f3dae4bb99db Author: Chris Lattner <sabre at nondot.org> Date:   Tue Feb 19 07:49:17 2008 +0000     remove the LowerSelect pass.  The last client was the old Sparc backend, which is long

Hi Martin, Pseudo CALLSEQ_START was changed in r302527, commit message contains details on the changes. However CALLSEQ_END was not modified. If your made changes to ADJCALLSTACKUP to add additional argument, that may result in error. Thanks, --Serge 2017-09-15 19:09 GMT+07:00 Martin J. O'Riordan via llvm-dev < llvm-dev at lists.llvm.org>: > Hi LLVM-Devs, > > I have managed

..."# OR_A_oo", [(set FPUaROUTADDRegisterClass:$FA_ROUTADD,(or FPUaOffsetOperand:$OffsetA,FPUaOffsetOperand:$OffsetB))],NoItinerary> {let usesCustomInserter = 1;} The instructions selection and registers allocation are performed with the pseudo. %4:fpuaoffsetclass = LOAD_A_r @a; FPUaOffsetClass:%4 %5:fpuaoffsetclass = LOAD_A_r @b; FPUaOffsetClass:%5 %6:fpuaroutaddregisterclass = OR_A_oo killed %5, killed %4, implicit-def dead...

Hi LLVM-Devs, I have managed to complete updating our sources from LLVM v4.0 to v5.0, but I am getting selection errors for 'callseq_end'. I am aware that the 'ADJCALLSTACKUP' and 'ADJCALLSTACKDOWN' patterns have changed, and have added an additional argument to the TD descriptions for these. There are interactions with 'ISD::CALL' and 'ISD::RET_FLAG',

...B); > + } > > // Copy0MBB: > // %FalseValue = ... > diff --git a/lib/Target/BPF/BPFInstrInfo.td b/lib/Target/BPF/BPFInstrInfo.td > index f683578..56f0f9c 100644 > --- a/lib/Target/BPF/BPFInstrInfo.td > +++ b/lib/Target/BPF/BPFInstrInfo.td > @@ -464,7 +464,7 @@ let usesCustomInserter = 1 in { > (ins GPR:$lhs, i64imm:$rhs, i64imm:$imm, > GPR:$src, GPR:$src2), > "# Select PSEUDO $dst = $lhs $imm $rhs ? $src : $src2", > [(set i64:$dst, > - (BPFselectcc i64:$lhs, (i64...

> LLVM's register coalescer and allocator don't try to reschedule > instructions, which seems to be required here. > I think you're right. Looking at the instruction schedules before register allocation, shows that it's scheduling the load before the zero move in one case but not the other. Is there an easy way I can trick the scheduler into putting these in the right

...ng something wrong? My goal is to provide an expansion for 64-bit division that unfortunately uses branches for a target that doesn't support 64-bit integers. Thanks, Javier On Thu, 10 Dec 2009 22:52:12 -0800, Evan Cheng <evan.cheng at apple.com> wrote: > See X86InstrInfo.td > let usesCustomInserter = 1, isTwoAddress = 0, Defs = [EFLAGS] in > def CMOV_GR8 : I<0, Pseudo, > > This creates a CMOV_GR8 pseudo instruction at isel time which can be > expanded during scheduling time. > > Evan > > On Dec 10, 2009, at 11:46 AM, Javier Martinez wrote: > >> Hello, &...

Hi, I've tagged the 5.0.1-rc2 release, go ahead and start testing and report your results. -Tom

Hi, I'm trying to implement __builtin_setjmp / __builtin_longjmp for Sparc processors. I think I'm very close, but I can't work out how to issue BuildMI-type instructions to load the address of the recovery location (set in setjmp) into a register using the SETHI / OR combination. I can't see any equivalent code anywhere else in Sparc. I imagine this is similar if I try to make a

...rt : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, *************** *** 447,452 **** --- 457,489 ---- [(set f128:$dst, (SPselectfcc f128:$T, f128:$F, imm:$Cond))]>; } + let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { + let Defs = [WIM] in + def EH_SJLJ_SETJMP32ri : Pseudo<(outs IntRegs:$dst), (ins MEMri:$buf), + "#EH_SJLJ_SETJMP32", + [(set i32:$dst, (SPsjlj_setjmp ADDRri:$buf))]>, + Requires<[Is...

...ONST : Constants; > + > +def FP_ZERO : PatLeaf < > + (fpimm), > + [{return N->getValueAPF().isZero();}] > +>; > + > +def FP_ONE : PatLeaf < > + (fpimm), > + [{return N->isExactlyValue(1.0);}] > +>; > + > +let isCodeGenOnly = 1, isPseudo = 1, usesCustomInserter = 1 in { > + > +class CLAMP <RegisterClass rc> : AMDGPUShaderInst < > + (outs rc:$dst), > + (ins rc:$src0), > + "CLAMP $dst, $src0", > + [(set rc:$dst, (int_AMDIL_clamp rc:$src0, (f32 FP_ZERO), (f32 FP_ONE)))] > +>; > + > +class FABS <Registe...