search for: userwarnflag

...$(call filechk,initramfs_list) quiet_cmd_cpio = CPIO $@ diff --git a/kernel/Kbuild.klibc b/kernel/Kbuild.klibc --- a/kernel/Kbuild.klibc +++ b/kernel/Kbuild.klibc @@ -31,8 +31,7 @@ KLIBSRC := usr/klibc # Arch specific definitions for klibc include $(KLIBSRC)/arch/$(ARCH)/MCONFIG -USERWARNFLAGS := -Wall -Wpointer-arith -Wwrite-strings \ - -Wstrict-prototypes -Winline +USERWARNFLAGS := -W -Wall -Wsign-compare USERCROSS := $(CROSS_COMPILE) @@ -48,9 +47,10 @@ USERCPPFLAGS := -I$(srctree)/usr/incl -I$(srctree)/usr/includ...

Hi Peter & others. Here are three patches that does the following: #1 - Update kbuild part of klibc so make clean works Adds gzip including a sample kbuild file #2 - Factor out definition of usr/ to two variables #3 - Move kbuild files to reflect location in the kernel As requested in earlier mail I need a bit of guidiance of what you expect from the kernel integrated parts of klibc.

...clude $(srctree)/scripts/Kbuild.include - -# Defines used when compiling early userspace (klibc programs) -# --------------------------------------------------------------------------- -KLIBSRC := usr/klibc - -# Arch specific definitions for klibc -include $(KLIBSRC)/arch/$(ARCH)/MCONFIG - -USERWARNFLAGS := -W -Wall -Wsign-compare - -USERCROSS := $(CROSS_COMPILE) - -USERLD := $(USERCROSS)ld -USERCC := $(USERCROSS)gcc -USERAR := $(USERCROSS)ar -USERRANLIB := $(USERCROSS)ranlib -USERSTRIP := $(USERCROSS)strip -USERNM := $(USERCROSS)nm - -USERCPP...

.../mpssd/Makefile > new file mode 100644 > index 0000000..eb860a7 > --- /dev/null > +++ b/Documentation/mic/mpssd/Makefile > @@ -0,0 +1,19 @@ > +# > +# Makefile - Intel MIC User Space Tools. > +# Copyright(c) 2013, Intel Corporation. > +# > +ifdef DEBUG > +CFLAGS += $(USERWARNFLAGS) -I. -g -Wall -DDEBUG=$(DEBUG) > +else > +CFLAGS += $(USERWARNFLAGS) -I. -g -Wall > +endif > + > +mpssd: mpssd.o sysfs.o > + $(CC) $(CFLAGS) -o $@ $^ -lpthread > + > +install: > + install mpssd /usr/sbin/mpssd > + install micctrl /usr/sbin/micctrl > + > +clean:...

.../mpssd/Makefile > new file mode 100644 > index 0000000..eb860a7 > --- /dev/null > +++ b/Documentation/mic/mpssd/Makefile > @@ -0,0 +1,19 @@ > +# > +# Makefile - Intel MIC User Space Tools. > +# Copyright(c) 2013, Intel Corporation. > +# > +ifdef DEBUG > +CFLAGS += $(USERWARNFLAGS) -I. -g -Wall -DDEBUG=$(DEBUG) > +else > +CFLAGS += $(USERWARNFLAGS) -I. -g -Wall > +endif > + > +mpssd: mpssd.o sysfs.o > + $(CC) $(CFLAGS) -o $@ $^ -lpthread > + > +install: > + install mpssd /usr/sbin/mpssd > + install micctrl /usr/sbin/micctrl > + > +clean:...

...a/Documentation/mic/mpssd/Makefile b/Documentation/mic/mpssd/Makefile new file mode 100644 index 0000000..eb860a7 --- /dev/null +++ b/Documentation/mic/mpssd/Makefile @@ -0,0 +1,19 @@ +# +# Makefile - Intel MIC User Space Tools. +# Copyright(c) 2013, Intel Corporation. +# +ifdef DEBUG +CFLAGS += $(USERWARNFLAGS) -I. -g -Wall -DDEBUG=$(DEBUG) +else +CFLAGS += $(USERWARNFLAGS) -I. -g -Wall +endif + +mpssd: mpssd.o sysfs.o + $(CC) $(CFLAGS) -o $@ $^ -lpthread + +install: + install mpssd /usr/sbin/mpssd + install micctrl /usr/sbin/micctrl + +clean: + rm -f mpssd *.o diff --git a/Documentation/mic/mpssd/micct...

ChangeLog: ========= v1 => v2: a) License wording cleanup, sysfs ABI documentation, patch 1 refactoring into 3 smaller patches and function renames, as per feedback from Greg Kroah-Hartman. b) Use VRINGH infrastructure for accessing virtio rings from the host in patch 5, as per feedback from Michael S. Tsirkin. v1: Initial post @ https://lkml.org/lkml/2013/7/24/810 Description:

ChangeLog: ========= v1 => v2: a) License wording cleanup, sysfs ABI documentation, patch 1 refactoring into 3 smaller patches and function renames, as per feedback from Greg Kroah-Hartman. b) Use VRINGH infrastructure for accessing virtio rings from the host in patch 5, as per feedback from Michael S. Tsirkin. v1: Initial post @ https://lkml.org/lkml/2013/7/24/810 Description:

ChangeLog: ========= v2 => v3: a) Patch 1 data structure cleanups, header file include cleanups, IDA interface reuse and switching to device_create_with_groups(..) as per feedback from Greg Kroah-Hartman. b) Patch 7 signal documentation, sleep workaround removal and sysfs access API cleanups as per feedback from Michael S. Tsirkin. v1 => v2: @ http://lwn.net/Articles/563131/ a)

ChangeLog: ========= v2 => v3: a) Patch 1 data structure cleanups, header file include cleanups, IDA interface reuse and switching to device_create_with_groups(..) as per feedback from Greg Kroah-Hartman. b) Patch 7 signal documentation, sleep workaround removal and sysfs access API cleanups as per feedback from Michael S. Tsirkin. v1 => v2: @ http://lwn.net/Articles/563131/ a)

ChangeLog: ========= v2 => v3: a) Patch 1 data structure cleanups, header file include cleanups, IDA interface reuse and switching to device_create_with_groups(..) as per feedback from Greg Kroah-Hartman. b) Patch 7 signal documentation, sleep workaround removal and sysfs access API cleanups as per feedback from Michael S. Tsirkin. v1 => v2: @ http://lwn.net/Articles/563131/ a)

ChangeLog: ========= v2 => v3: a) Patch 1 data structure cleanups, header file include cleanups, IDA interface reuse and switching to device_create_with_groups(..) as per feedback from Greg Kroah-Hartman. b) Patch 7 signal documentation, sleep workaround removal and sysfs access API cleanups as per feedback from Michael S. Tsirkin. v1 => v2: @ http://lwn.net/Articles/563131/ a)

An Intel MIC X100 device is a PCIe form factor add-in coprocessor card based on the Intel Many Integrated Core (MIC) architecture that runs a Linux OS. It is a PCIe endpoint in a platform and therefore implements the three required standard address spaces i.e. configuration, memory and I/O. The host OS loads a device driver as is typical for PCIe devices. The card itself runs a bootstrap after

An Intel MIC X100 device is a PCIe form factor add-in coprocessor card based on the Intel Many Integrated Core (MIC) architecture that runs a Linux OS. It is a PCIe endpoint in a platform and therefore implements the three required standard address spaces i.e. configuration, memory and I/O. The host OS loads a device driver as is typical for PCIe devices. The card itself runs a bootstrap after