Displaying 7 results from an estimated 7 matches for "useoffset".
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useoffsets
2014 Jul 05
1
[PATCH 1/2] nvc0/ir: use manual TXD when offsets are involved
...ivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -769,7 +769,8 @@ NVC0LoweringPass::handleTXD(TexInstruction *txd)
if (dim > 2 ||
txd->tex.target.isCube() ||
arg > 4 ||
- txd->tex.target.isShadow())
+ txd->tex.target.isShadow() ||
+ txd->tex.useOffsets)
return handleManualTXD(txd);
for (int c = 0; c < dim; ++c) {
--
1.8.5.5
2014 Apr 04
2
[PATCH 1/2] nvc0: add support for texture gather
...s/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -744,9 +744,15 @@ NVC0LoweringPass::handleTEX(TexInstruction *i)
int s = i->srcCount(0xff, true);
if (i->srcExists(s)) // move potential predicate out of the way
i->moveSources(s, 1);
- for (n = 0; n < i->tex.useOffsets; ++n)
+ if (i->op == OP_TXG) {
+ assert(i->tex.useOffsets == 1);
for (c = 0; c < 3; ++c)
- value |= (i->tex.offset[n][c] & 0xf) << (n * 12 + c * 4);
+ value |= (i->tex.offset[0][c] & 0xff) << (c * 8);
+ } else {
+...
2014 Feb 04
1
[PATCH] nouveau/codegen: allow tex offsets on non-TXF instructions (e.g. TXL)
..._OPCODE_SAMPLE_C_LZ)
texi->tex.levelZero = true;
+ for (s = 0; s < tgsi.getNumTexOffsets(); ++s) {
+ for (c = 0; c < 3; ++c) {
+ texi->tex.offset[s][c] = tgsi.getTexOffset(s).getValueU32(c, info);
+ if (texi->tex.offset[s][c])
+ texi->tex.useOffsets = s + 1;
+ }
+ }
+
bb->insertTail(texi);
}
--
1.8.3.2
2015 Jan 04
0
[PATCH] nv50/ir: fix texture offsets in release builds
...vers/nouveau/codegen/nv50_ir_lowering_nv50.cpp
index e283424..0d7612e 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nv50.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nv50.cpp
@@ -772,7 +772,8 @@ NV50LoweringPreSSA::handleTEX(TexInstruction *i)
if (i->tex.useOffsets) {
for (int c = 0; c < 3; ++c) {
ImmediateValue val;
- assert(i->offset[0][c].getImmediate(val));
+ if (!i->offset[0][c].getImmediate(val))
+ assert(!"non-immediate offset");
i->tex.offset[c] = val.reg.data.u32;...
2014 Mar 20
0
[PATCH] nvc0/ir: move sample id to second source arg to fix sampler2DMS
...i->setSrc(0, src);
}
+ // for nvc0, the sample id ends up being treated as an offset, so we can't
+ // do offset and ms at the same time. on nve0, the sample id is part of the
+ // texture coordinate argument.
+ assert(chipset >= NVISA_GK104_CHIPSET ||
+ !i->tex.useOffsets || !i->tex.target.isMS());
+
// offset is last source (lod 1st, dc 2nd)
if (i->tex.useOffsets) {
uint32_t value = 0;
@@ -741,7 +748,7 @@ NVC0LoweringPass::handleTEX(TexInstruction *i)
i->setSrc(s, bld.loadImm(NULL, value));
}
- if (prog->getTarget()->ge...
2014 Aug 08
2
[PATCH 1/3] nvc0/ir: add base tex offset for fermi indirect tex case
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
.../drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
index f010767..4a9e48f 100644
---
2014 Sep 25
0
[PATCH] gm107/ir: fix texture argument order
...tex->tex.target.getArgCount() - tex->tex.target.isMS();
+ if (tex->op == OP_TXD) {
+ // Indirect handle belongs in the first arg
+ if (tex->tex.rIndirectSrc >= 0)
+ s++;
+ if (!tex->tex.target.isArray() && tex->tex.useOffsets)
+ s++;
+ }
n = tex->srcCount(0xff) - s;
} else {
s = tex->srcCount(0xff);
--
1.8.5.5