Displaying 3 results from an estimated 3 matches for "useidx".
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useid
2016 Nov 27
5
Extending Register Rematerialization
...hysicalRegister(MO.getReg())) {
if (MRI.isConstantPhysReg(MO.getReg(),
*DefMI->getParent()->getParent()))
continue;
//If not constant then check its def
if(depth > 6)
return false;
LiveInterval &li = LIS.getInterval(MO.getReg());
SlotIndex UseIdx = LIS.getInstructionIndex(*DefMI);
VNInfo *UseVNInfo = li.getVNInfoAt(UseIdx);
MachineInstr *NewDefMI = LIS.getInstructionFromIndex(UseVNInfo->def);
if(!checkComplexRematerializable(UseVNInfo, NewDefMI, depth+1, aa))
return false;
}
}
Remattable.insert(VNI);...
2013 Apr 30
1
[LLVMdev] Instruction Scheduling - migration from v3.1 to v3.2
...ual int TargetInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
const MachineInstr *DefMI, unsigned DefIdx,
const MachineInstr *UseMI,
unsigned UseIdx) const;
virtual unsigned TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
const MachineInstr *MI,
unsigned *PredCost = 0) const;
Example:
def CortexA8Model : SchedMachineModel...
2016 Jun 08
2
Instruction Itineraries: question about operand latencies
I overrode getInstrLatency and did some printing to see what is available
there. It looks like the registers are still virtual at that point when
getInstrLatency is called - is that correct? (we needed to make some
decisions based on actual registers that have been assigned since some
registers are reserved as address space pointers and we could vary the
latency based on which address space