Displaying 12 results from an estimated 12 matches for "us72".
Did you mean:
us2
2013 Jan 29
2
[LLVMdev] Apparent indeterminism in PreVerifier
...he
following:
Common predecessor:
*** IR Dump After Loop-Closed SSA Form Pass ***
for.body.us68: ; preds =
%for.body.lr.ph.us81, %for.body.us68
%arrayidx.us70.phi = phi i8* [ %buf.0.ph, %for.body.lr.ph.us81 ], [
%arrayidx.us70.inc, %for.body.us68 ]
%add.ptr4.us72.phi = phi i8* [ %add.ptr4.us72.gep, %for.body.lr.ph.us81 ],
[ %add.ptr4.us72.inc, %for.body.us68 ]
%i.043.us69 = phi i32 [ 0, %for.body.lr.ph.us81 ], [ %inc.us73,
%for.body.us68 ]
...
LV: Found a vectorizable loop (8) in core_state.i
LV: Adding RT check for range: %add.ptr4.us72.phi = phi i8*...
2013 Jan 29
2
[LLVMdev] Apparent indeterminism in PreVerifier
...Dump After Loop-Closed SSA Form Pass ***
>> for.body.us68: ; preds =
>> %for.body.lr.ph.us81, %for.body.us68
>> %arrayidx.us70.phi = phi i8* [ %buf.0.ph, %for.body.lr.ph.us81 ], [
>> %arrayidx.us70.inc, %for.body.us68 ]
>> %add.ptr4.us72.phi = phi i8* [ %add.ptr4.us72.gep,
>> %for.body.lr.ph.us81 ], [ %add.ptr4.us72.inc, %for.body.us68 ]
>> %i.043.us69 = phi i32 [ 0, %for.body.lr.ph.us81 ], [ %inc.us73,
>> %for.body.us68 ]
>> ...
>>
>> LV: Found a vectorizable loop (8) in core_state.i
>>...
2013 Jan 29
0
[LLVMdev] Apparent indeterminism in PreVerifier
...>
> *** IR Dump After Loop-Closed SSA Form Pass ***
> for.body.us68: ; preds =
> %for.body.lr.ph.us81, %for.body.us68
> %arrayidx.us70.phi = phi i8* [ %buf.0.ph, %for.body.lr.ph.us81 ], [
> %arrayidx.us70.inc, %for.body.us68 ]
> %add.ptr4.us72.phi = phi i8* [ %add.ptr4.us72.gep,
> %for.body.lr.ph.us81 ], [ %add.ptr4.us72.inc, %for.body.us68 ]
> %i.043.us69 = phi i32 [ 0, %for.body.lr.ph.us81 ], [ %inc.us73,
> %for.body.us68 ]
> ...
>
> LV: Found a vectorizable loop (8) in core_state.i
> LV: Adding RT check for r...
2013 Jan 29
0
[LLVMdev] Apparent indeterminism in PreVerifier
...Loop-Closed SSA Form Pass ***
> >> for.body.us68: ; preds =
> >> %for.body.lr.ph.us81, %for.body.us68
> >> %arrayidx.us70.phi = phi i8* [ %buf.0.ph, %for.body.lr.ph.us81 ], [
> >> %arrayidx.us70.inc, %for.body.us68 ] %add.ptr4.us72.phi = phi i8* [
> >> %add.ptr4.us72.gep,
> >> %for.body.lr.ph.us81 ], [ %add.ptr4.us72.inc, %for.body.us68 ]
> >> %i.043.us69 = phi i32 [ 0, %for.body.lr.ph.us81 ], [ %inc.us73,
> >> %for.body.us68 ]
> >> ...
> >>
> >> LV: Found a vec...
2013 Jan 29
1
[LLVMdev] Apparent indeterminism in PreVerifier
...SSA Form Pass ***
>>>> for.body.us68: ; preds =
>>>> %for.body.lr.ph.us81, %for.body.us68
>>>> %arrayidx.us70.phi = phi i8* [ %buf.0.ph, %for.body.lr.ph.us81 ], [
>>>> %arrayidx.us70.inc, %for.body.us68 ] %add.ptr4.us72.phi = phi i8* [
>>>> %add.ptr4.us72.gep,
>>>> %for.body.lr.ph.us81 ], [ %add.ptr4.us72.inc, %for.body.us68 ]
>>>> %i.043.us69 = phi i32 [ 0, %for.body.lr.ph.us81 ], [ %inc.us73,
>>>> %for.body.us68 ]
>>>> ...
>>>>
>>>...
2013 Jan 07
0
[LLVMdev] instruction scheduling issue
Liu,
This is likely a better solution for you - you do not want to mess with
the scheduler unless you really have to ;)
Sergei
---
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by
The Linux Foundation
> -----Original Message-----
> From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu]
> On Behalf Of Krzysztof Parzyszek
> Sent:
2013 Jan 07
4
[LLVMdev] instruction scheduling issue
On 1/7/2013 2:15 PM, Xu Liu wrote:
>
> This would be ideal. How can I do the instrumentation pass after the
> instruction scheduling?
You could derive your own class from TargetPassConfig, and add the
annotation pass in YourDerivedTargetPassConfig::addPreEmitPass. This
will add your annotation pass very late, just before the final code is
emitted. If you're using the X86 target,
2013 Mar 01
2
[LLVMdev] Interesting post increment situation in DAG combiner
...*
%p.next_loopiv.us67 = add nsw i32 %p.loopiv48.us66, 4 <<<<<<<<<<<<<<<<<<
IV
%_p_vec_full.us71 = load <4 x i16>* %vector_ptr.us70, align 16
<<<<<<<<<<<<<<<<<<<Load
%add5p_vec.us72 = add <4 x i16> %_p_vec_full.us71, %5
store <4 x i16> %add5p_vec.us72, <4 x i16>* %vector_ptr.us70, align 16
<<<<<<<<<<<<<<<Store
%p_arrayidx.us69.inc = getelementptr i16* %p_arrayidx.us69.phi, i32 4
<<<<<<<<...
2013 Mar 01
0
[LLVMdev] Interesting post increment situation in DAG combiner
...dd nsw i32 %p.loopiv48.us66, 4
> <<<<<<<<<<<<<<<<<<
> IV
> %_p_vec_full.us71 = load <4 x i16>* %vector_ptr.us70, align 16
> <<<<<<<<<<<<<<<<<<<Load
> %add5p_vec.us72 = add <4 x i16> %_p_vec_full.us71, %5
> store <4 x i16> %add5p_vec.us72, <4 x i16>* %vector_ptr.us70, align
> 16
> <<<<<<<<<<<<<<<Store
> %p_arrayidx.us69.inc = getelementptr i16* %p_arrayidx.us69.phi, i32
> 4
>...
2013 Mar 01
1
[LLVMdev] Interesting post increment situation in DAG combiner
...66, 4
> > <<<<<<<<<<<<<<<<<<
> > IV
> > %_p_vec_full.us71 = load <4 x i16>* %vector_ptr.us70, align 16
> > <<<<<<<<<<<<<<<<<<<Load
> > %add5p_vec.us72 = add <4 x i16> %_p_vec_full.us71, %5
> > store <4 x i16> %add5p_vec.us72, <4 x i16>* %vector_ptr.us70, align
> > 16
> > <<<<<<<<<<<<<<<Store
> > %p_arrayidx.us69.inc = getelementptr i16* %p_arrayidx.us69.p...
2013 Mar 01
0
[LLVMdev] parallel loop metadata simplification
----- Original Message -----
> From: "Paul Redmond" <paul.redmond at intel.com>
> To: "llvmdev at cs.uiuc.edu Dev" <llvmdev at cs.uiuc.edu>
> Sent: Thursday, February 28, 2013 1:30:57 PM
> Subject: [LLVMdev] parallel loop metadata simplification
>
> Hi,
>
> I've been working on clang codegen for #pragma ivdep and creating the
>
2013 Feb 28
5
[LLVMdev] parallel loop metadata simplification
Hi,
I've been working on clang codegen for #pragma ivdep and creating the llvm.mem.parallel_loop_access metadata seems quite difficult. The main problem is that there are so many places where loads and stores are created and all of them need to be changed when emitting a parallel loop. Note that creating llvm.loop.parallel is not a problem.
One option is to modify IRBuilder to enable