search for: updateregallochint

Displaying 2 results from an estimated 2 matches for "updateregallochint".

[LLVMdev] How to specify that Src Reg and Dest Reg can't be the same in td?
2012 Jul 13
2
[LLVMdev] How to specify that Src Reg and Dest Reg can't be the same in td?
Hi all, I would like to know if XXXInstrInfo.td or other td files should be the right place to specify Src Reg and Dest Reg in one instruction can't be the same. If so, could you give an example on that? Thanks! Regards, chenwj -- Wei-Ren Chen (陳韋任) Computer Systems Lab, Institute of Information Science, Academia Sinica, Taiwan (R.O.C.) Tel:886-2-2788-3799 #1667 Homepage:
[LLVMdev] How to specify that Src Reg and Dest Reg can't be the same in td?
2012 Jul 13
0
[LLVMdev] How to specify that Src Reg and Dest Reg can't be the same in td?
Hi Wei-Ren, I don't think you can model it with Constraints in td files. You may try to put a regalloc hint in src and dst operands of the instructions you are interested. See getRawAllocationOrder(), ResolveRegAllocHint() and UpdateRegAllocHint() hooks in TargetRegisterInfo. ARM has good examples on how to implements them. Ivan On 13/07/2012 09:28, 陳韋任 (Wei-Ren Chen) wrote: > Hi all, > > I would like to know if XXXInstrInfo.td or other td files should be > the right place to specify Src Reg and Dest Reg in one instructio...