Displaying 6 results from an estimated 6 matches for "uo_f32".
2012 Dec 13
0
[LLVMdev] RTLIB::UO_F32
what C code would produce the following when soft float is enabled?
(RTLIB::UO_F32, "__unordsf2");
(RTLIB::UO_F64, "__unorddf2");
(RTLIB::O_F32, "__unordsf2");
(RTLIB::O_F64, "__unorddf2");
tia.
reed
2012 Dec 14
0
[LLVMdev] RTLIB::UO_F32
Hi Reed,
Sorry about the off-list reply. I need to reset my list preferences.
If I build:
cmp.c:
int cmp_single(float a) { return (a != a) ? 1 : 0; }
int cmp_double(double a) { return (a != a) ? 1 : 0; }
with clang -target mips-unknown -S cmp.c
I get calls to __unordsf2 and __unorddf2.
Pete
2009 Jun 22
1
[LLVMdev] Floating point comparison doubt
Hi,
In unordered floating point comparison before making a call for
comparison proper one node called UO_F32 is generated. In targets this
node is replaced with a call to __unordsf2.
My doubts here
1) What are these UO_F32 and O_F32 nodes for?
2) What is this function (__unordsf2) supposed to do?
Regards
Sachin
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2009 May 21
0
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On Wed, May 20, 2009 at 4:55 PM, Dan Gohman <gohman at apple.com> wrote:
> Can you explain why you chose the approach of using a new pass?
> I pictured removing LegalizeDAG's type legalization code would
> mostly consist of finding all the places that use TLI.getTypeAction
> and just deleting code for handling its Expand and Promote. Are you
> anticipating something more
2009 May 20
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On May 20, 2009, at 1:34 PM, Eli Friedman wrote:
> On Wed, May 20, 2009 at 1:19 PM, Eli Friedman
> <eli.friedman at gmail.com> wrote:
>
>> Per subject, this patch adding an additional pass to handle vector
>>
>> operations; the idea is that this allows removing the code from
>>
>> LegalizeDAG that handles illegal types, which should be a significant
2009 May 21
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
...case ISD::SETOLE:
- LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
- break;
- case ISD::SETGT:
- case ISD::SETOGT:
- LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
- break;
- case ISD::SETUO:
- LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
- break;
- case ISD::SETO:
- LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
- break;
- default:
- LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
- switch (cast<CondCodeSDNode>(CC)->get()) {
- case ISD::SET...