search for: unwindless

....bc -debug-pass=Structure Pass Arguments: -lowergc -lowerinvoke -lowerswitch -unreachableblockelim Target Data Layout Module Pass Manager Function Pass Manager Lower GC intrinsics, for GCless code generators -- Lower GC intrinsics, for GCless code generators Lower invoke and unwind, for unwindless code generators -- Lower invoke and unwind, for unwindless code generators Lower SwitchInst's to branches -- Lower SwitchInst's to branches Remove unreachable blocks from the CFG -- Remove unreachable blocks from the CFG X86 Pattern Instruction Selection -- X86 Pattern Instr...

...ass Arguments: -lowergc -lowerinvoke -lowerswitch -unreachableblockelim > Target Data Layout > Module Pass Manager > Function Pass Manager > Lower GC intrinsics, for GCless code generators > -- Lower GC intrinsics, for GCless code generators > Lower invoke and unwind, for unwindless code generators > -- Lower invoke and unwind, for unwindless code generators > Lower SwitchInst's to branches > -- Lower SwitchInst's to branches > Remove unreachable blocks from the CFG > -- Remove unreachable blocks from the CFG > X86 Pattern Instruction Sele...

...rinvoke -lowerswitch -unreachableblockelim > > Target Data Layout > > Module Pass Manager > > Function Pass Manager > > Lower GC intrinsics, for GCless code generators > > -- Lower GC intrinsics, for GCless code generators > > Lower invoke and unwind, for unwindless code generators > > -- Lower invoke and unwind, for unwindless code generators > > Lower SwitchInst's to branches > > -- Lower SwitchInst's to branches > > Remove unreachable blocks from the CFG > > -- Remove unreachable blocks from the CFG > >...

...rength Reduction -- ET Forest Construction -- Scalar Evolution Analysis -- Canonicalize natural loops -- Loop Strength Reduction -- Natural Loop Construction Lower GC intrinsics, for GCless code generators -- Lower GC intrinsics, for GCless code generators Lower invoke and unwind, for unwindless code generators -- Lower invoke and unwind, for unwindless code generators Remove unreachable blocks from the CFG -- Remove unreachable blocks from the CFG X86 DAG->DAG Instruction Selection -- X86 DAG->DAG Instruction Selection **************** Due to my register allocator *******...

...nstruction > -- Scalar Evolution Analysis > -- Canonicalize natural loops > -- Loop Strength Reduction > -- Natural Loop Construction > Lower GC intrinsics, for GCless code generators > -- Lower GC intrinsics, for GCless code generators > Lower invoke and unwind, for unwindless code generators > -- Lower invoke and unwind, for unwindless code generators > Remove unreachable blocks from the CFG > -- Remove unreachable blocks from the CFG > X86 DAG->DAG Instruction Selection > -- X86 DAG->DAG Instruction Selection > **************** Due to m...

...lution Analysis > > -- Canonicalize natural loops > > -- Loop Strength Reduction > > -- Natural Loop Construction > > Lower GC intrinsics, for GCless code generators > > -- Lower GC intrinsics, for GCless code generators > > Lower invoke and unwind, for unwindless code generators > > -- Lower invoke and unwind, for unwindless code generators > > Remove unreachable blocks from the CFG > > -- Remove unreachable blocks from the CFG > > X86 DAG->DAG Instruction Selection > > -- X86 DAG->DAG Instruction Selection >...

On Tue, 2005-07-26 at 17:25 -0700, Michael McCracken wrote: > Since I'm modifying llc, I have a couple small questions about that code: > > opt and analyze (and a couple of other places) add a verifier pass, > but llc doesn't. > This would seem to make sense for llc as well - should I add it, with > the corresponding > hidden -no-verify option? I can't see any

On 7/25/05, Reid Spencer <reid at x10sys.com> wrote: > On Mon, 2005-07-25 at 21:48 -0700, Michael McCracken wrote: > > On 7/25/05, Reid Spencer <reid at x10sys.com> wrote: > > > Why not just create your pass as a shared object and: > > > > > > opt -load mypass.so -mypass | llc > > > > My pass is an implementation of an analysis group that

...output(float %22, i32 5)   %23 = extractelement <4 x float> %9, i32 2   call void @llvm.AMDGPU.store.output(float %23, i32 6)   %24 = extractelement <4 x float> %9, i32 3   call void @llvm.AMDGPU.store.output(float %24, i32 7)   ret void } *** IR Dump Before Lower invoke and unwind, for unwindless code generators *** define void @main() {   call void @llvm.AMDGPU.reserve.reg(i32 0)   call void @llvm.AMDGPU.reserve.reg(i32 1)   call void @llvm.AMDGPU.reserve.reg(i32 2)   call void @llvm.AMDGPU.reserve.reg(i32 3)   %1 = call float @llvm.R600.load.input(i32 4)   %2 = insertelement <4 x float...

...i32> undef, i32 %54, i32 0   %56 = insertelement <1 x i32> undef, i32 %29, i32 0   %57 = shufflevector <1 x i32> %56, <1 x i32> %55, <1 x i32> <i32 1>   %58 = extractelement <1 x i32> %57, i32 0   br label %25 } *** IR Dump Before Lower invoke and unwind, for unwindless code generators *** define void @main() {   call void @llvm.AMDGPU.reserve.reg(i32 0)   call void @llvm.AMDGPU.reserve.reg(i32 1)   call void @llvm.AMDGPU.reserve.reg(i32 2)   call void @llvm.AMDGPU.reserve.reg(i32 3)   %1 = call float @llvm.AMDGPU.load.const(i32 0)   %2 = bitcast float %1 to i32  ...

...; %56 = insertelement <1 x i32> undef, i32 %29, i32 0 > %57 = shufflevector <1 x i32> %56, <1 x i32> %55, <1 x i32> <i32 1> > %58 = extractelement <1 x i32> %57, i32 0 > br label %25 > } > *** IR Dump Before Lower invoke and unwind, for unwindless code generators *** > define void @main() { > call void @llvm.AMDGPU.reserve.reg(i32 0) > call void @llvm.AMDGPU.reserve.reg(i32 1) > call void @llvm.AMDGPU.reserve.reg(i32 2) > call void @llvm.AMDGPU.reserve.reg(i32 3) > %1 = call float @llvm.AMDGPU.load.const(i32...