search for: unspillable

This shortens runtime of piglit test fp-long-alu to ~22s No piglit regressions observed on nvc0! Signed-off-by: Tobias Klausmann <tobias.johannes.klausmann at mni.thm.de> --- src/gallium/drivers/nouveau/codegen/nv50_ir.cpp | 6 +++--- src/gallium/drivers/nouveau/codegen/nv50_ir.h | 7 ++++--- src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 2 +-

...ReMatDefs. %reg1461 is created for one of the spill intervals of %reg1235. It is marked as rematerializable with defining instruction: %reg1235<def> = FsMOVLPDrm %reg1097, 1, %reg1364, 8, Mem:LD(8,8) [tmp17641765 + 0] Note that this is the same instruction as above. %reg1097 is marked unspillable (weight set to HUGE_VALF). %reg1461 gets assigned XMM15 by the register allocator. Later on %reg1364 is spilled and assigned a stack slot. When rewriting instructions after regalloc, we come across this instruction: %XMM3<def> = MOVSDrr %reg1461, %R12<imp-use> %reg1461 was marked a...

Hi Christoph, bin/shader_runner tests/spec/glsl-1.40/uniform_buffer/fs-struct-copy-complicated.shader_test -auto bin/shader_runner tests/spec/glsl-1.40/uniform_buffer/vs-struct-copy-complicated.shader_test -auto bin/shader_runner tests/spec/glsl-1.50/uniform_buffer/gs-struct-copy-complicated.shader_test -auto Now all segfault. I reverted 2e9ee44797 ("nv50/ir/ra: some register spilling

Hi! I'm developing a register allocator that works iteratively. It spills some virtual registers on each iteration until all the rest have physical ones assigned. How can I spill some live intervals at the end of each iteration with new live intervals having correct weights? Thanks. -------------- next part -------------- An HTML attachment was scrubbed... URL:

...developing a register allocator that works iteratively. It spills some > virtual registers on each iteration until all the rest have physical ones > assigned. Take a look at the linear scan allocator. It is also iterative: it uses the spiller interface to insert spill code, which creates (unspillable) intervals for the spill code it inserts. > How can I spill some live intervals at the end of each iteration with new > live intervals having correct weights? The linscan allocator inserts spill code with infinite weight, take a look at how it works. -Chris -- http://nondot.org/sabre/...

...ing this for all live intervals of this regclass, I'm filtering only the ones that dont have a small size (returned by li.getSize()) > > Does this possible cause make any sense at all? Yes, that sounds like a workable fix. It is important that live ranges coming out of the spiller are unspillable, but the zero length intervals don't need an infinite spill weight - very very large is good enough. > In either case, in the meantime, I can live with this workaround until an official fix is implemented. I'll fill in a bug report to track this problem so you can take a look at it when...

I'm not sure about one thing: you assign stack slot to each new register you replace the spilled one with. And then you need to allocate physical registers to them. Is it possible to assign physical register to the virtual one which has a stack slot already? On 8/21/06, Fernando Magno Quintao Pereira <fernando at cs.ucla.edu> wrote: > > > > So what addIntervalsToSpills

Hello to all LLVM developers. I'm developing a register allocator using LLVM, my allocator has a local search phase: given a solution (assignment of virtual registers to physical registers or memory) generated in the first phase of the algorithm, some movements are applied to this solution in order to find a better solution. To apply such movements, I need to unassign a virtual register from

...sing alloca to allocate/denote space for local variables, and then optimize those into SSA values when optimization proves that is OK. Also, for a lot of things, that attribute is simply impossible to implement. Any value that is live across a call needs to be spilled to memory. You cannot put an unspillable value in a callee preserved register, because you cannot know whether the callee may save that or not. And if it is in a caller-save register, then the caller has to spill it if it is live across a call. Kevin B. Smith -----Original Message----- From: llvm-dev [mailto:llvm-dev-bounces at lists.ll...

...hysreg with a virtreg that is live across the inline asm. This is not easy to detect without a bad compile time regression. I suppose something similar could happen for calls. For instance, some calls clobber all XMM registers, so a physical XMM register coalesced to be live across a call would be unspillable. What can I say? Physreg coalescing is evil ;-) I want to remove physreg coalescing entirely, but it requires the register allocator to be really good at taking hints. We are not quite there yet. A quick fix would be to disable physreg coalescing for functions containing inline asm. /jakob

Ok, I've found that marking tiny live intervals as not spillable inside VirtRegAuxInfo::CalculateWeightAndHint is not playing nicely with very constrained regclasses, in my case a regclass composed of only one register. As a workaround, instead of marking them as not spillable, I've marked them with a very high spill cost and the regalloc is able to compile the function with good code

...gister (problem.isPRegOption(vreg, alloc)), - or a spill (problem.isSpillOption(vreg, alloc)) The problem is that pass CalcSpillWeights can 'hint' that it is a poor idea to spill this specific register with : CalcSpillWeights.cpp / VirtRegAuxInfo::CalculateWeightAndHint : // Mark li as unspillable if all live ranges are tiny. if (li.isZeroLength(LIS.getSlotIndexes())) { li.markNotSpillable(); ... This hint makes the register non spillable at all for the spiller (that's the assert above), not just a bad-idea-to-spill-but-feasible. The pbqp allocator does not cope with this di...

See http://llvm.org/bugs/show_bug.cgi?id=4668 and http://llvm.org/bugs/show_bug.cgi?id=5010. The basic description of the issue (from http://llvm.org/bugs/show_bug.cgi?id=4668#c5): "The fundamental problem is we can't spill a register once it's fixed to a physical register." >From discussion on IRC: [17:14] <_sabre_> efriedma: sounds like a RA bug in linscan [17:14]

https://bugs.freedesktop.org/show_bug.cgi?id=96258 Bug ID: 96258 Summary: [NVC0] Hang when running compute program Product: Mesa Version: git Hardware: Other OS: All Status: NEW Severity: normal Priority: medium Component: Drivers/DRI/nouveau Assignee: nouveau at

Thanks, I think that's a useful way to look at it (though if I wanted to bikeshed I'd suggest the name "DoubleIndirect" as a bit more precise than "VeryIndirect"). An aspect of it that I'm still puzzling over is that my target runtime (at least in its current form) doesn't have a way to represent/process a "VeryIndirect" pointer. So I'd like to

To recap, this is what I was trying to solve: This C code: int bar(int a, int b, int c, int d, int e, int f); int foo(int a, int b, int c, int d, int e ) { int x = 3*a; return bar3(a,b,c,d,e,x); } Produced the following assembly output: foo: push {r11, lr} sub sp, #8 bl bar add sp, #8 pop {r11, pc} The part I didn't like is that push/pop become

Sorry to reply to myself here, but I had an idea regarding "issue #2" -- possibly what makes the most sense for those clients/targets is to pull the pointer difference computation/reapplication into RS4GC itself -- it could have a pass just before or after rematerialization, which runs based on a configuration flag (eventually to be driven by GCStrategy), which performs rewrites like

...that works iteratively. It spills > some > > virtual registers on each iteration until all the rest have physical > ones > > assigned. > > Take a look at the linear scan allocator. It is also iterative: it uses > the spiller interface to insert spill code, which creates (unspillable) > intervals for the spill code it inserts. > > > How can I spill some live intervals at the end of each iteration with > new > > live intervals having correct weights? > > The linscan allocator inserts spill code with infinite weight, take a look > at how it works....

https://bugs.freedesktop.org/show_bug.cgi?id=90348 Bug ID: 90348 Summary: Spilling failure of b96 merged value Product: Mesa Version: git Hardware: Other OS: All Status: NEW Severity: normal Priority: medium Component: Drivers/DRI/nouveau Assignee: nouveau at

...t the patch, which I think means deciding that there's only 1 bundle for w15. Does anyone know where and how exactly these bundles are decided? * Try and change how evicted / split registers are allocated in some way. Things I've tried: * In RAGreedy::enqueue reduce the score of unspillable local intervals, and in RAGreedy::evictInterference put evicted registers into stage RS_Split immediately. This causes %381 to be split immediately instead of being requeued, and then makes %391 have a higher score than %253 causing it to be allocated before it. This works, but ends...