Displaying 5 results from an estimated 5 matches for "unpcklpd".
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unpcklps
2013 Jul 19
0
[LLVMdev] llvm.x86.sse2.sqrt.pd not using sqrtpd, calling a function that modifies ECX
...,xmm2
002E04F8 addpd xmm0,xmm1
002E04FC addpd xmm2,xmm7
002E0500 movsd xmm4,mmword ptr ds:[2E0090h]
002E0508 movapd xmm1,xmm4
002E050C divsd xmm1,xmm2
002E0510 unpckhpd xmm2,xmm2
002E0514 movapd xmm3,xmm4
002E0518 divsd xmm3,xmm2
002E051C unpcklpd xmm1,xmm3
002E0520 mulpd xmm1,xmmword ptr ds:[2E00A0h]
002E0528 addpd xmm1,xmm0
002E052C movapd xmm3,xmmword ptr [esp+0A0h]
002E0535 movapd xmm0,xmm3
002E0539 unpckhpd xmm0,xmm0
002E053D movapd xmm2,xmm3
002E0541 movapd xmm6,xmm3
002E0545 addsd...
2015 Jan 04
2
[LLVMdev] Heads up! Planning to remove old vector shuffle lowering this week...
On Sun, Jan 4, 2015 at 3:20 PM, Simon Pilgrim <llvm-dev at redking.me.uk>
wrote:
> On 24 Nov 2014, at 17:53, Chandler Carruth <chandlerc at gmail.com> wrote:
>
> > I'll be skimming the PRs to see if there are any really critical
> regressions, but so far it looks pretty good.
> >
> > If you are actively disabling the new vector shuffling and have some PR
2011 Dec 28
1
[LLVMdev] Codegen for vector float->double cast fails on x86 above SSE3
...loat> vector from %in, fpext cast it to a
<2 x double>, and do an unaligned store (movupd) of the result to
%out. This works as expected on earlier SSE targets, generating this
with llc -mcpu=core2:
movss (%rdi), %xmm1
movss 4(%rdi), %xmm0
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
unpcklpd %xmm0, %xmm1 ## xmm1 = xmm1[0],xmm0[0]
movupd %xmm1, (%rsi)
ret
Load both, cast float to double (cvtss2sd), pack vectors, and store.
But with llc -mcpu=penryn or greater, it yields nonsense:
movq (%rdi), %xmm0
pshufd $16, %xmm0, %xmm0 ## xmm0 = xmm0[0,0,1,0]
movdqu %xmm0, (%rsi)
r...
2013 Jul 19
4
[LLVMdev] SIMD instructions and memory alignment on X86
Hmm, I'm not able to get those .ll files to compile if I disable SSE and I
end up with SSE instructions(including sqrtpd) if I don't disable it.
On Thu, Jul 18, 2013 at 10:53 PM, Peter Newman <peter at uformia.com> wrote:
> Is there something specifically required to enable SSE? If it's not
> detected as available (based from the target triple?) then I don't think
2015 Jan 05
3
[LLVMdev] Heads up! Planning to remove old vector shuffle lowering this week...
....
Thanks,
Q.
>
> The amount of domain crossing is much lower now - but there are a number of float shuffles that now use double shuffles instead - fine from a domain point of view but rather unexpected. IIRC this often appeared in matrix transpose code - movlhps / movhlps being replaced by unpcklpd / unpckhpd is the one I seem to remember.
>
> Overall - a massive improvement - thank you!
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