search for: unmodelled

Hi A bunch of instructions that I have defined in tablegen files get tagged with unmodeledSideEffect property. I have defined these instructions with no corresponding dag patterns. Is there a way i can avoid this property and say they do not have any side effects thanks shrey

> On Mar 21, 2016, at 9:14 PM, Mehdi Amini via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > >> On Mar 21, 2016, at 8:58 AM, Nicolai Hähnle <nhaehnle at gmail.com> wrote: >> >> On 19.03.2016 16:25, Mehdi Amini wrote: >>> Hi, >>> >>> Can you elaborate what is the impact at the IR level? >>> If the point is just about

----- Original Message ----- > Hi Matt, > > On Nov 8, 2013, at 1:14 PM, Matt Arsenault > <Matthew.Arsenault at amd.com> wrote: > > > Both of these I think sort of went in the wrong direction and > > talked specifically about the semantics of the atomic instructions > > (fence in particular), which isn't the real question. Is noalias > > supposed

Hal, > While I think that it will be relatively easy to have the intrinsics > serve as code-motion barriers for other code that might be threads > sensitive (like other external function calls), we would need to think > through exactly how this would work. The easiest thing would be to make > the intrinsics have having unmodeled side effects, although we might > want to do

Andrey, Are you still working on this? Thanks again, Hal ----- Original Message ----- > From: "Hal Finkel" <hfinkel at anl.gov> > To: "Andrey Bokhanko" <andreybokhanko at gmail.com> > Cc: llvmdev at cs.uiuc.edu > Sent: Wednesday, October 10, 2012 12:19:32 AM > Subject: Re: [LLVMdev] [RFC] OpenMP Representation in LLVM IR > > > >

----- Original Message ----- > From: "Andrey Bokhanko" <andreybokhanko at gmail.com> > To: "Hal Finkel" <hfinkel at anl.gov> > Cc: llvmdev at cs.uiuc.edu > Sent: Wednesday, October 3, 2012 3:15:54 AM > Subject: Re: [LLVMdev] [RFC] OpenMP Representation in LLVM IR > > Hal, > > > While I think that it will be relatively easy to have the

> On Nov 8, 2013, at 6:32 PM, Hal Finkel <hfinkel at anl.gov> wrote: > > ----- Original Message ----- >> Hi Matt, >> >> On Nov 8, 2013, at 1:14 PM, Matt Arsenault >> <Matthew.Arsenault at amd.com> wrote: >> >>> Both of these I think sort of went in the wrong direction and >>> talked specifically about the semantics of the

Hal, Our proposal is effectively got scrapped by the community, so we are not pushing any further on the approach we proposed before. How about meeting at the LLVM conference to discuss this? Yours, Andrey On Mon, Nov 5, 2012 at 11:05 PM, Hal Finkel <hfinkel at anl.gov> wrote: > Andrey, > > Are you still working on this? > > Thanks again, > Hal > > ----- Original

...rich Weigand wrote: > C) Floating-point exceptions > If a mask bit in the floating-point status register is set, then all FP > instructions will *trap* whenever an IEEE exception condition is > recognized. This means that we need to treat those instructions as > having unmodelled side effects, so that they cannot be speculatively > executed. Also, we cannot schedule FP instructions across instructions Does this mean that the problems with the default expansion of ISD::FP_TO_UINT would be solved by the backend knowing that it should model traps? In D43515 the issue o...

Hello all, I want to add a custom intrinsic to the LLVM IR which would be lowered into a pseudo instruction since it doesn't correspond to any real instruction defined by the architecture. The speciality of this intrinsic/pseudo instruction that it should behave like a scheduling barrier: every instruction before the intrinsic has to be emitted before the intrinsic, the same goes for all

I'm trying to figure out how to use lmer to fit models with factors that have some nesting and some non-nested groupings. For example, in this paper: http://www.stat.columbia.edu/~gelman/research/published/parkgelmanbafumi.pdf we have a logistic regression of survey respondents' political preferences (1=Republican, 0=Democrat), regressing on sex, ethnicity, state (51 states within 5

Sent from my iPhone > On Nov 8, 2013, at 6:32 PM, Hal Finkel <hfinkel at anl.gov> wrote: > > ----- Original Message ----- >> Hi Matt, >> >> On Nov 8, 2013, at 1:14 PM, Matt Arsenault >> <Matthew.Arsenault at amd.com> wrote: >> >>> Both of these I think sort of went in the wrong direction and >>> talked specifically about the

Resending; I accidentally dropped llvm-dev. -Eli From: Eli Friedman Sent: Wednesday, April 1, 2020 1:01 PM To: Ten Tzen <tentzen at microsoft.com> Cc: aaron.smith at microsoft.com Subject: RE: [EXT] [llvm-dev] [RFC] [Windows SEH] Local_Unwind (Jumping out of a _finally) and -EHa (Hardware Exception Handling) This looks like it outlines the implementation pretty well. For goto in finally,

...enceable while > the other is? In other words, does dereferenceability depend on > the addrspace of the pointer given that the "location" is > dereferenceable? In our architecture, address space casts will never trap and are deterministic (unless there is some asm with unmodelled side effects). However, there are pointers that can be dereferenced in one address space but not another: speculatively performing the load would be a real bug. Ideally, this would be a target-specific decision, but having the default be to not propagate the dereferencing information and allowing...

I think we're going to need to create a new mechanism to communicate strict FP modes to the backend. I think we need to avoid doing anything that will require re-inventing or duplicating all of the pattern matching that goes on in instruction selection (which is the reason we're currently dropping that information). I'm out of my depth on this transition, but I think maybe we could

Reply inline From: Ten Tzen <tentzen at microsoft.com> Sent: Wednesday, April 1, 2020 3:54 PM To: Eli Friedman <efriedma at quicinc.com>; llvm-dev <llvm-dev at lists.llvm.org> Cc: aaron.smith at microsoft.com Subject: [EXT] RE: [llvm-dev] [RFC] [Windows SEH] Local_Unwind (Jumping out of a _finally) and -EHa (Hardware Exception Handling) ? For goto in finally, why are you

Hi all, I'm a grad student from MIT and as part of my thesis, I will be propagating parallelism in the IR level. I will be modifying clang and adding LLVM IR metadata annotations to indicate parallel regions and loops, then write optimizer passes that will run on top of the annotated LLVM IR. There has been a lot of research lately on Parallel IRs, such as SPIR[1

Hello, at the recent EuroLLVM developer meeting in Bristol I held a BoF session on the topic "Towards implementing #pragma STDC FENV_ACCESS". I've also had a number of follow-on discussions both on-site in Bristol and online since. This post is intended as a summary of my current understanding set of requirements and implementation details covering the overall topic. I'm

On 2011-06-26, at 8:44 AM, Jakob Stoklund Olesen wrote: > On Jun 25, 2011, at 11:39 PM, Cameron Zwarich wrote: > >> Someone hit a bug (not in bugs.llvm.org) caused by the non-Darwin call instructions not being marked as using the frame pointer. Is it safe to just add r11 / r7 as uses to the appropriate instructions like we do on Darwin? Does anyone care about the slight pessimization

Hi Ulrich, I am interested in knowing if the current proposals also take into account the FP_CONTRACT pragma and the ability to implement options that imply a specific value for the FLT_EVAL_METHOD macro. Additionally, I am not aware of the IR being able to represent the potentially deferred loss of precision that the C language semantics provide; in particular, applying such semantics to the