search for: unk12

...earch this BYPASS_PLL_CHECK in Nvidia traces but seemed it wasn't used nowhere for CLK settings. Removing this works fine, but I don't know what it's really for. Actual bit setting this BYPASS_PLL_CHECK is on 0x10: lookup -ac0 0x137000 0x10 PCLOCK.CLK0_CTRL => { BYPASS_PLL_CHECK | UNK12 = 0 } Also, disabling this bit on other CLKs doesn't seem to break anything. v2: Add back PLL lock test Signed-off-by: Mark Menzynski <mmenzyns at redhat.com> --- drm/nouveau/nvkm/subdev/clk/gf100.c | 1 - drm/nouveau/nvkm/subdev/clk/gk104.c | 1 - 2 files changed, 2 deletions(-) diff...

Create the ref_bo without any storage type flags set for now. The issue probably arises from our use of the additional buffer space at the end of the ref_bo. It should probably be split up in the future. Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> Tested-by: Martin Peres <martin.peres at labri.fr> Cc: "10.0" <mesa-stable at lists.freedesktop.org> ---

...earch this BYPASS_PLL_CHECK in Nvidia traces but seemed it wasn't used nowhere for CLK settings. Removing this works fine, but I don't know what it's really for. Actual bit setting this BYPASS_PLL_CHECK is on 0x10: lookup -ac0 0x137000 0x10 PCLOCK.CLK0_CTRL => { BYPASS_PLL_CHECK | UNK12 = 0 } Also, disabling this bit on other CLKs doesn't seem to break anything. v2: add back PLL lock test v3: add restoring original value after PLL lock test Signed-off-by: Mark Menzynski <mmenzyns at redhat.com> --- drm/nouveau/nvkm/subdev/clk/gf100.c | 7 +++++-- drm/nouveau/nvkm/subd...

...earch this BYPASS_PLL_CHECK in Nvidia traces but seemed it wasn't used nowhere for CLK settings. Removing this works fine, but I don't know what it's really for. Actual bit setting this BYPASS_PLL_CHECK is on 0x10: lookup -ac0 0x137000 0x10 PCLOCK.CLK0_CTRL => { BYPASS_PLL_CHECK | UNK12 = 0 } Also, disabling this bit on other CLKs doesn't seem to break anything. Tested with GF119 NVS 310. Signed-off-by: Mark Menzynski <mmenzyns at redhat.com> --- drm/nouveau/nvkm/subdev/clk/gf100.c | 8 -------- drm/nouveau/nvkm/subdev/clk/gk104.c | 8 -------- 2 files changed, 16 dele...

...earch this BYPASS_PLL_CHECK in Nvidia traces but seemed it wasn't used nowhere for CLK settings. Removing this works fine, but I don't know what it's really for. Actual bit setting this BYPASS_PLL_CHECK is on 0x10: lookup -ac0 0x137000 0x10 PCLOCK.CLK0_CTRL => { BYPASS_PLL_CHECK | UNK12 = 0 } Also, disabling this bit on other CLKs doesn't seem to break anything. v2: add back PLL lock test v3: add restoring original value after PLL lock test v4: read the bit with nvkm_mask Signed-off-by: Mark Menzynski <mmenzyns at redhat.com> --- drm/nouveau/nvkm/subdev/clk/gf100.c |...

...0 0..6 -> buffer id > // tmp_idx is the index of the associated co-located motion data buffer > // for simplest management, ensure that this is always equal to the buffer id > unsigned tmp_idx : 5; // 00 7..11 > unsigned unk12 : 1; // 00 12 not seen yet, but set, maybe top_is_reference -> top_is_reference > unsigned unk13 : 1; // 00 13 not seen yet, but set, maybe bottom_is_reference? -> bottom_is_reference > unsigned unk14 : 1; // 00 14 skipped? -> is_long_term >...

On Thu, Nov 21, 2013 at 5:22 PM, Ilia Mirkin <imirkin at alum.mit.edu> wrote: > On Thu, Nov 21, 2013 at 5:07 PM, Benjamin Morris <bmorris at nvidia.com> wrote: >> On 11/19/2013 08:16 PM, Ilia Mirkin wrote: >>> Hello, >>> >>> I hope this is an appropriate style of request for this forum. I added >>> code to support video decoding on the tesla

...e that was saved.. unsigned fifo_idx : 7; // 00 0..6 -> buffer id // tmp_idx is the index of the associated co-located motion data buffer // for simplest management, ensure that this is always equal to the buffer id unsigned tmp_idx : 5; // 00 7..11 unsigned unk12 : 1; // 00 12 not seen yet, but set, maybe top_is_reference -> top_is_reference unsigned unk13 : 1; // 00 13 not seen yet, but set, maybe bottom_is_reference? -> bottom_is_reference unsigned unk14 : 1; // 00 14 skipped? -> is_long_term unsigned notseenyet : 1; // 00 15 pad? -> not...

On Thu, May 21, 2015 at 10:05 AM, Robert Morell <rmorell at nvidia.com> wrote: > Hi Ilia, > > On Sat, May 02, 2015 at 12:34:21PM -0400, Ilia Mirkin wrote: >> Hi, >> >> As I'm looking to add some support to nouveau for features like atomic >> counters and images, I'm running into some confusion about what the >> first word of the shader header

...08.303395 MMIO32 R 0x610b94 0x00000000 PDISPLAY.DAC_VAL_MODE_CTRL2[0x2][0x1] => 0 [0] 108.303409 MMIO32 R 0x610ad0 0x00824414 PDISPLAY.CRTC_VAL[0].CLOCK[0] => 0x824414 [0] 108.303425 MMIO32 W 0x614100 0x10000611 PDISPLAY.CLOCK.VPLL_CTRL1[0] <= { UNK0 = 0x11 | STAGES = 2 | CONNECTED = 0x3 | UNK12 = 0 | UNK23 = 0 | UNK28 } [0] 108.303439 MMIO32 R 0x614104 0x00020016 PDISPLAY.CLOCK.VPLL_S1[0] => { N1 = 0x16 | M1 = 0x2 } [0] 108.303452 MMIO32 W 0x614104 0x00020016 PDISPLAY.CLOCK.VPLL_S1[0] <= { N1 = 0x16 | M1 = 0x2 } [0] 108.303466 MMIO32 R 0x614108 0x2007000e PDISPLAY.CLOCK.VPLL_S2[0] =...

As it turns out, with the proprietary firmware, the VP3 and VP4 interfaces are identical. Furthermore, this is all already implemented for nvc0. So these patches (a) move the easily sharable bits of the nvc0 implementation into the nouveau directory, and then (b) implement the other parts in nv50. The non-shared parts are still largely copies, but there are some differences, not the least of which