search for: uncond

...s my code. #Creating dataframes new.data2<-expand.grid(FCOND=23.5, FPC1=-0.68, MCOND=22.4, MPC1=-0.82, RANK=c(6:15)) new.data3<-expand.grid(FOCND=39.1, FPC1=0.46, MCOND=7.4, MPC1=1.3, RANK=c(4:16)) x2<-data.frame(mod.avg.pred=c(0.28, 0.26, 0.24, 0.23, 0.22, 0.21, 0.20, 0.19, 0.19, 0.18), uncond.se=c(0.17, 0.15, 0.14, 0.14, 0.15, 0.16, 0.18, 0.19, 0.20, 0.21)) x3<-data.frame(mod.avg.pred=c(0.19, 0.22, 0.26, 0.32, 0.39, 0.47, 0.54, 0.61, 0.66, 0.70, 0.73, 0.75, 0.77), uncond.se=c(0.18, 0.17, 0.16, 0.14, 0.13, 0.14, 0.18, 0.22, 0.24, 0.26, 0.27, 0.28, 0.28)) #creating a graph that works...

...t; generates for my TargetMachine to try to reconstruct high-level flow > control. > > I misunderstood the isTerminator property of an instruction to mean > that it had to be at the end of a basic block, but now I've seen > blocks that end with a conditional branch followed by an unconditional > branch. > > I'm sure this depends somewhat on my target, but can there be an > arbitrary number of conditional branches before that last branch? How > about before a return? Right now, the interface assumes that a block ending with a branch has at most two successors (s...

...ructions that LLVM generates for my TargetMachine to try to reconstruct high-level flow control. I misunderstood the isTerminator property of an instruction to mean that it had to be at the end of a basic block, but now I've seen blocks that end with a conditional branch followed by an unconditional branch. I'm sure this depends somewhat on my target, but can there be an arbitrary number of conditional branches before that last branch? How about before a return? Before I dive in and generalize my analysis (probably only a minor pain), is there any way I can get LLVM to gen...

...you look at the other CFG it's just run with default clang opts (ie clang source_file) and all it's doing is lowering the switch (the same problem still exists). Seems confusing to me? ps. Round has no control flow logic in it and when the loop is unrolled there is no control flow at all (uncond branching, etc). The logic gets even more convoluted when simplycfg and other opts are applied. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120913/31afcd9d/attachment.html> -------------- next part ---...

...ls a function that cannot return. Insert an // unreachable instruction after it and simplify the code. Do this // by splitting the BB, adding the unreachable, then deleting the // new BB. BasicBlock *New = BB->splitBasicBlock(I); // Remove the uncond branch and add an unreachable. BB->getInstList().pop_back(); new UnreachableInst(BB->getContext(), &*BB); DeleteBasicBlock(New, CG); // Delete the new BB. MadeChange = true; ++NumUnreach; break; } The nested if in Simp...

According to the docs, InsertBranch should only be called if AnalyzeBranch returns success. But in targets (like ARM or Sparc) that don't implement them, the following test fails: ----------------------------------- void %__gcov_init() { entry: switch uint 0, label %cond_true.i [ uint 0, label %UnifiedReturnBlock uint 875573313, label