Displaying 6 results from an estimated 6 matches for "umulo".
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2018 Feb 28
2
How to handle UMULO?
Hi All,
While compiling libgcc, I find I have to deal with UMULO (overflow-aware
unsigned multiplication) SDNode. UMULO returns the result of
multiplication, and a boolean indicating overflow occurred or not. Our
target's multiply instruction doesn't care (detect) overflow. I am
wondering if I can always set the boolean to false. I am not sure about
this...
2018 Feb 28
1
How to handle UMULO?
...l need to do the more complicated check in the boundary cases, I think.
--paulr
From: llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] On Behalf Of Bruce Hoult via llvm-dev
Sent: Wednesday, February 28, 2018 5:43 AM
To: 陳韋任
Cc: LLVM Developers Mailing List
Subject: Re: [llvm-dev] How to handle UMULO?
I think your users will be very upset if you don't set the boolean return value correctly :-)
Whatever work it takes to determine the correct value for it, if the user code doesn't need/use that value then the dead code will be eliminated later. But if they need that return flag then the...
2018 Feb 28
0
How to handle UMULO?
...adds (again detecting
carry/overflow, but that's easier for addition).
It all depends on what instructions your target has.
On Wed, Feb 28, 2018 at 4:31 PM, 陳韋任 via llvm-dev <llvm-dev at lists.llvm.org>
wrote:
> Hi All,
>
> While compiling libgcc, I find I have to deal with UMULO (overflow-aware
> unsigned multiplication) SDNode. UMULO returns the result of
> multiplication, and a boolean indicating overflow occurred or not. Our
> target's multiply instruction doesn't care (detect) overflow. I am
> wondering if I can always set the boolean to false. I am...
2008 Dec 09
1
[LLVMdev] [PATH] Add sub.ovf/mul.ovf intrinsics
Hi,
The attached patch implements sub.ovf/mul.ovf intrinsics similarly to
the recently added add.ovf intrinsics. These are useful for
implementing some vm instructions like sub.ovf/mul.ovf in .NET IL
efficiently. sub.ovf is supported in target independent lowering and
on x86, while mul.ovf is only supported in the x86 backend.
Please review
2014 Jul 09
3
[LLVMdev] Signed/Unsigned Instruction selection.
The sign information for binary operators is available in the llvm IR by the
'nsw' (no signed wrap) flag. Seems there is no use of this flag in the code
generation phase.
The sign information is no more available in the selection DAG.
So how can I generate different instructions for binary operators with
signed/unsigned operands in the assembler (e.g. mul/mulu)?
--
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2012 Jul 16
3
[LLVMdev] RFC: LLVM incubation, or requirements for committing new backends
...e Num = Op.getOperand(0);
> + SDValue Den = Op.getOperand(1);
> +
> + SmallVector<SDValue, 8> Results;
> +
> + // RCP = URECIP(Den) = 2^32 / Den + e
> + // e is rounding error.
> + SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den);
> +
> + // RCP_LO = umulo(RCP, Den) */
> + SDValue RCP_LO = DAG.getNode(ISD::UMULO, DL, VT, RCP, Den);
> +
> + // RCP_HI = mulhu (RCP, Den) */
> + SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);
> +
> + // NEG_RCP_LO = -RCP_LO
> + SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.g...