Displaying 5 results from an estimated 5 matches for "umullohi".
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umul_lohi
2016 Jan 18
2
Using `smullohi` in TableGen patterns
I’m hitting TableGen errors trying to match the smullohi <lhs> <rhs> node
in TableGen.
smullohi returns two results, which is the problem. I am not sure how to
match against multiple results. The only other nodes to return two operands
are umullohi, udivrem, and sdivrem. There are no examples of these in
TableGen in tree.
The closest I can get is this:
set (R1, R0, (umullohi GPR8:$lhs, GPR8:$rhs))
Which fails:
Assertion failed: (Ops.size() >= NumSrcResults && "Didn't
provide enough results"), funct...
2016 Jan 18
3
Using `smullohi` in TableGen patterns
...g> wrote:
>
> I’m hitting TableGen errors trying to match the smullohi <lhs> <rhs> node
> in TableGen.
>
> smullohi returns two results, which is the problem. I am not sure how to
> match against multiple results. The only other nodes to return two operands
> are umullohi, udivrem, and sdivrem. There are no examples of these in
> TableGen in tree.
>
> The closest I can get is this:
>
> set (R1, R0, (umullohi GPR8:$lhs, GPR8:$rhs))
>
>
> As far as I know, you cannot define a tablegen pattern with multiple
> results, and need to use...
2009 May 21
0
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On Wed, May 20, 2009 at 4:55 PM, Dan Gohman <gohman at apple.com> wrote:
> Can you explain why you chose the approach of using a new pass?
> I pictured removing LegalizeDAG's type legalization code would
> mostly consist of finding all the places that use TLI.getTypeAction
> and just deleting code for handling its Expand and Promote. Are you
> anticipating something more
2009 May 20
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On May 20, 2009, at 1:34 PM, Eli Friedman wrote:
> On Wed, May 20, 2009 at 1:19 PM, Eli Friedman
> <eli.friedman at gmail.com> wrote:
>
>> Per subject, this patch adding an additional pass to handle vector
>>
>> operations; the idea is that this allows removing the code from
>>
>> LegalizeDAG that handles illegal types, which should be a significant
2009 May 21
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
...}
- if (HasMULHS) {
- // We can emit a mulhs+mul.
- Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
- Hi = DAG.getNode(ISD::MULHS, dl, NVT, LL, RL);
- break;
- }
- }
- if (HasUMUL_LOHI) {
- // Lo,Hi = umul LHS, RHS.
- SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl,
- DAG.getVTList(NVT, NVT), LL, RL);
- Lo = UMulLOHI;
- Hi = UMulLOHI.getValue(1);
- RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
- LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
- Hi = DAG.get...