search for: uint8

...detailed frame record: Clients require more information about the function frame, such as spilled registers, etc. The frame base register i.e. might change when dynamic stack realignment is performed on X86. If there is anything missing please let me know. Thanks Cheers, Juergen Header v2 { uint8 : Stack Map Version (2) uint8 : Reserved [3] (0) uint32 : Constants Offset (bytes) uint32 : Frame Records Offset (bytes) uint32 : Frame Registers Offset (bytes) uint32 : StackMap Records Offset (bytes) uint32 : Locations Offset (bytes) uint32 : LiveOuts Offset (bytes) } align to 8...

...;offset:187;encoding:uint;format:hex;set:Floating > Point Registers;#00 > $qRegisterInfo52#a9 > $name:mxcsrmask;bitsize:32;offset:191;encoding:uint;format:hex;set:Floating > Point Registers;#00 > $qRegisterInfo53#aa > $name:stmm0;bitsize:80;offset:195;encoding:vector;format:vector-uint8;set:Floating > Point Registers;gcc:33;dwarf:33;#00 > $qRegisterInfo54#ab > $name:stmm1;bitsize:80;offset:205;encoding:vector;format:vector-uint8;set:Floating > Point Registers;gcc:34;dwarf:34;#00 > $qRegisterInfo55#ac > $name:stmm2;bitsize:80;offset:215;encoding:vector;format:vect...

Thank you, Clayton. This is very helpful. We use the LLDB specific GDB remote extensions, and our debugger server supports "qRegisterInfo" package. "reg 0x3c" is the frame pointer. In the example mentioned above, we have SP = FP - 40 for current call frame. And variable "a" is stored at address (FP + -24) from asm instruction [FP + -24] = R3;; Thus we can conclude

hi, the current release_20 branch seems to miscompile the following reduced testcase (not target architecture specific): #define UInt16 unsigned short #define UInt8 unsigned char UInt8 foo(UInt16 a) { return (UInt8)(((a >> 10) & 1) << 1); } it - misleadingly - optimizes the expression to something like (undef & 2). I guess the problem is related to the DAG combiner but I haven't done a thorough analysis yet. a quick search didn'...

...ion frame, such as spilled registers, etc. The frame base register i.e. might change when dynamic stack > realignment is performed on X86. > > > If there is anything missing please let me know. > > Thanks > > Cheers, > Juergen > > > Header v2 { > uint8 : Stack Map Version (2) > uint8 : Reserved [3] (0) > uint32 : Constants Offset (bytes) > uint32 : Frame Records Offset (bytes) > uint32 : Frame Registers Offset (bytes) > uint32 : StackMap Records Offset (bytes) > uint32 : Locations Offset (bytes) > uint32 : Liv...

Hi, I've found a test case where SelectionDAG is doing an undefined behavior optimization, and I need help determining whether or not this is legal. Here is the example IR: define void @test(<4 x i8> addrspace(1)* %out, float %a) { %uint8 = fptoui float %a to i8 %vec = insertelement <4 x i8> <i8 0, i8 0, i8 0, i8 0>, i8 %uint8, i32 0 store <4 x i8> %vec, <4 x i8> addrspace(1)* %out ret void } Since %vec is a 32-bit vector, a common way to implement this function on a target with 32-bit registers would...

...e, when I used to do x86 SIMD optimization for a living, I did similar tricks pretty much everywhere in DSP functions. It’d be pretty nice if the compiler could do it too. There is one alternate approach that I recall, which looks like this: Original code (example, pseudocode): int add_delta_256(uint8 *in1, uint8 *in2) { int accum = 0; for (int i = 0; i < 16; ++i) { uint8x16 a = load16(in1 + i *16); // NOTE: takes an extra addressing op because x86 uint8x16 b = load16(in2 + i *16); // NOTE: takes an extra addressing op because x86 accum += psadbw(a, b); } return accum; } end...

On 08/26/2011 05:32, Stephan Falke wrote: > As stated in LLVM's language reference manual > (http://llvm.org/docs/LangRef.html#i_shl), both arguments for a shl need > to have the same type. In my case, original types were uint8 (value) and uint32 (shift) llvm lacks unsigned types which made it S1=i8 and S2=i32. It's technically nothing wrong with such combination, and code works fine until I ran debug llvm for some other reason and this assert showed up. So if I need to shift signed int8 with unsigned uint32, I hav...

On Wed, 30 May 2007, Dietmar Ebner wrote: > the current release_20 branch seems to miscompile the following reduced > testcase (not target architecture specific): > > #define UInt16 unsigned short > #define UInt8 unsigned char > UInt8 foo(UInt16 a) { > return (UInt8)(((a >> 10) & 1) << 1); > } > > it - misleadingly - optimizes the expression to something like (undef & > 2). I guess the problem is related to the DAG combiner but I haven't > done a thorough analys...

Hi, I made a patch against branch-1.0 for SHA256 password hashing support for Dovecot. Courier Authlib supports this hashing scheme and in order to migrate from Courier to Dovecot, I've added SHA256 support to Dovecot. The attached patch is based on BSD licensed code from Olivier Gay (http://www.ouah.org/ogay/sha2/). Changes made by me in Olivier's sha2{.h,.c} code: - Prototype for

...; norm <- (norm-min(norm)) / max(norm-min(norm)) > img <- outer(outer(norm, norm), norm) > img <- round(255 * img) > img[17:32,,] <- 255 - img[17:32,,] > img.nifti <- nifti(img) # create NIfTI object > > writeNIfTI(img.nifti, "test-nifti-image-uint8", verbose=TRUE) niftiExtension detected! niftiAuditTrail detected! vox_offset = 1392 *writing niftiExtension(s) at byte = 6.803919e+17 # <- LARGE NUMBER! writing data at byte = 6.803919e+17 # <- LARGE NUMBER!* > ## These files should be viewable in, for example, FSLv...

...) Out[4]: array([255, 1, 255]) As you can see, the G component was increased from 0 to 1. Those routines are the same as here: http://msdn.microsoft.com/en-us/library/ms893078.aspx Now let's try floating point conversions: In [3]: RGB2YCbCr_precise(a) Out[3]: array([106, 202, 222], dtype=uint8) In [4]: YCbCr2RGB_precise(RGB2YCbCr_precise(a)) Out[4]: array([255, 0, 254], dtype=uint8) This time the B component was decreased by 1... Those floating point routines were done by me, and I followed the theora spec. So my questions are: * does anyone here have a code, that can convert back...

...asses of memory. So, I'm wondering if anyone has any better ideas than what I'm doing - well, anything that would make a sizable difference anyway. Right now, my methodology is the following: Use mmap (from library mmap) to map the file to a memory mapped variable, reading in each byte as uint8 integer. obj <- mmap("file.txt", mode = uint8()) tmp <- obj[bytepos] Converting the integer representations of each byte into the appropriate integer by tmp <- tmp - 48 - 7*(tmp>64) Collating blocksize values together by tmp<- matrix(tmp, ncol = blocksize, byrow = T) %*% 1...

Hi Chanwit, What problems did you have for compiling the latest revision? Could you give me a log? Thanks, Nicolas On Thu, Jul 8, 2010 at 10:05 PM, Chanwit Kaewkasi <chanwit at gmail.com> wrote: > Thank you, Nicolas. > But I still have no luck compiling the latest revision. However, > vmkit-0.27 is compiled and running fine on my machine. > > Thanks, > > Chanwit >

I am attempting to implement a minor loop strength reduction optimization for targets that support compare and jump fusion, specifically TTI::canMacroFuseCmp(). My approach might be wrong; however, I am soliciting the idea for feedback, so that I can implement this correctly. My plan is to add a Supplemental LSR formula to LoopStrengthReduce.cpp that optimizes the following case, but perhaps

...nce string curve name ec_point Q string application uint64 serial uint32 type string key id string valid principals uint64 valid after uint64 valid before string critical options string extensions string reserved string signature key string signature string application uint8 flags string key_handle string reserved If the instant was to avoid duplicating what was already in the certificate, though, I?m not sure why ?application? is sent twice. It seems like that should have been left out along with the curve_id and Q value, appending only the flags, key_handle, and...

...+ +#ifndef __XEN_H__ +#define __XEN_H__ + +#include <Uefi/UefiBaseType.h> + +// Physical address of OVMF info +#define OVMF_INFO_PHYSICAL_ADDRESS 0x00001000 + +// This structure must match the definition on Xen side +#pragma pack(1) +typedef struct { + CHAR8 Signature[14]; // XenHVMOVMF\0 + UINT8 Length; // Length of this structure + UINT8 Checksum; // Set such that the sum over bytes 0..length == 0 + // + // Physical address of an array of TablesCount elements. + // + // Each element contains the physical address of a BIOS table. + // + EFI_PHYSICAL_ADDRESS Tables; + UI...

I get an assert @ Instructions.cpp:1774 when Op=llvm::Instruction::Shl. Should this assert avoid shift operations? Yuri

Hi Yuri, As stated in LLVM's language reference manual (http://llvm.org/docs/LangRef.html#i_shl), both arguments for a shl need to have the same type. What exactly are you trying to do? --Stephan > I get an assert @ Instructions.cpp:1774 when Op=llvm::Instruction::Shl. > Should this assert avoid shift operations? > > Yuri

...;host' => host.object_id) cpu properties used: cpunum corenum numcores vendor model family cpuid_lvl speed cache flags[0..251] New Matahari changed the model, here are CPU-related properties from 0.4.0 Host object, there isn't separate cpu class anymore: processors uint8 ReadOnly The number of physical CPUs. cores uint8 ReadOnly The total number of processor cores. model long-string ReadOnly The processor(s) model description. "model" is descriptive string, s...