Displaying 5 results from an estimated 5 matches for "uimm2".
2019 Nov 22
2
Tablegen PAT limitation?
...nbsp; list<Predicate> Predicates = [];
string DecoderMethod = "";
bit hasCompleteDecoder = 1;
string Namespace = "RPP";
dag OutOperandList = (outs);
dag InOperandList = (ins MGPR:$rs1, SGPR32:$rbase, MGPR:$roffset, uimm2:$rshift);
string AsmString = "STORE $rs1, [$rbase + ( $roffset << $rshift )]";
list<dag> Pattern = [(store (v1i16 ?:$rs1), (add (v1i32 (bitconvert (i32 ?:$rbase))), (shl (v1i32 (sext (v1i16 ?:$roffset))), (v1i32 (build_vector (uimm2 ?:$rshift))))))];...
2019 Nov 25
2
Tablegen PAT limitation?
...gen being unable to match the rs1 in the pattern with any of the instruction operands.
Could you change the pattern to
[(OpNode (v1i16 MGPR:$rs1), (add (v1i32 (bitconvert (i32 SGPR32:$rbase))), (shl (v1i32 (sext (v1i16 MGPR:$roffset))), (v1i32 (build_vector (i32 uimm2:$rshift))) )))]
--
Krzysztof Parzyszek kparzysz at quicinc.com AI tools development
From: Celine <595602881 at qq.com>
Sent: Thursday, November 21, 2019 7:59 PM
To: Krzysztof Parzyszek <kparzysz at quicinc.com>; llvm-d...
2019 Nov 21
2
Tablegen PAT limitation?
Hi Krzysztof,
Today I try it on llvm9.0.0 version.
def bos : RPPInstMMEMrr<OPC_STORE,
(outs), (ins MGPR:$rs1, SGPR32:$rbase, MGPR:$roffset, uimm2:$rshift),
!strconcat(opcodestr, ""), "$rs1, [$rbase + ( $roffset << $rshift )]",
// [(OpNode v1i16...
2019 Nov 20
4
Tablegen PAT limitation?
...art (../../../bin/llvm-tblgen+0x407bd9)
===========================================================
PATTERN: (st v1i16:{ *:[v1i16] }:$rs1, (add:{ *:[v1i32] } (shl:{ *:[v1i32] } (sext:{ *:[v1i32] } v1i16:{ *:[v1i16] }:$roffset), (build_vector:{ *:[v1i32] } (imm:{ *:[i32] })<<P:Predicate_uimm2>>:$rshift)), (bitconvert:{ *:[v1i32] } i32:{ *:[i32] }:$rbase)))<<P:Predicate_unindexedstore>><<P:Predicate_store>>
RESULT: (STOREbos v1i16:{ *:[v1i16] }:$rs1, i32:{ *:[i32] }:$rbase, v1i16:{ *:[v1i16] }:$roffset, (imm:{ *:[i32] }):$rs...
2019 Sep 27
2
Maybe a TableGen bug?
...0, 0, 0, 0, 0, 0, 0 };
field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
string Namespace = "ABC";
dag OutOperandList = (outs GPR_OUT:$rs1);
dag InOperandList = (ins SGPR32:$rbase, MGPR_ST:$roffset, uimm2:$rshift);
string AsmString = "LOAD [$rbase + ( $roffset << $rshift )], $rs1";
list<dag> Pattern = [(set i16v:$rs1, (load (add i32:$rbase, (shl (*sext
(i16 (bitconvert i16v:$roffset))*), i32:$rshift))))];
.....
i16v is a new type we added, same as i16, only name differ.
Wh...