Displaying 3 results from an estimated 3 matches for "uglygep2021".
2010 Sep 07
3
[LLVMdev] MachineMemOperand and dependence information
...nds are lost when two LDRs are combined
and a LDRD is generated in ARMPreAllocLoadStoreOpt:::RescheduleOps.
(before optimization)
%reg1033<def> = LDR %reg1030, %reg0, 4100, pred:14, pred:%reg0;
mem:LD4[%uglygep10]
%reg1054<def> = LDR %reg1030, %reg0, 4104, pred:14, pred:%reg0;
mem:LD4[%uglygep2021]
(after optimization)
%reg1054<def>, %reg1033<def> = LDRD %reg1030, %reg0, 264, pred:14,
pred:%reg0
Are there any reasons they need to be removed?
Would it break something if both MachineMemOperands were added to the newly
generated instruction?
(after optimization)
%reg1054<def&g...
2010 Sep 07
0
[LLVMdev] MachineMemOperand and dependence information
...o LDRs are combined and a LDRD is generated in ARMPreAllocLoadStoreOpt:::RescheduleOps.
>
> (before optimization)
> %reg1033<def> = LDR %reg1030, %reg0, 4100, pred:14, pred:%reg0; mem:LD4[%uglygep10]
> %reg1054<def> = LDR %reg1030, %reg0, 4104, pred:14, pred:%reg0; mem:LD4[%uglygep2021]
>
> (after optimization)
> %reg1054<def>, %reg1033<def> = LDRD %reg1030, %reg0, 264, pred:14, pred:%reg0
>
> Are there any reasons they need to be removed?
> Would it break something if both MachineMemOperands were added to the newly generated instruction?
>
&g...
2010 Sep 07
1
[LLVMdev] MachineMemOperand and dependence information
...D is generated in ARMPreAllocLoadStoreOpt:::RescheduleOps.
> >
> > (before optimization)
> > %reg1033<def> = LDR %reg1030, %reg0, 4100, pred:14, pred:%reg0;
> mem:LD4[%uglygep10]
> > %reg1054<def> = LDR %reg1030, %reg0, 4104, pred:14, pred:%reg0;
> mem:LD4[%uglygep2021]
> >
> > (after optimization)
> > %reg1054<def>, %reg1033<def> = LDRD %reg1030, %reg0, 264, pred:14,
> pred:%reg0
> >
> > Are there any reasons they need to be removed?
> > Would it break something if both MachineMemOperands were added to the
>...