search for: ucode_unload

...GM204 and GM206 signed firmware nvidia: Add GM20B signed firmware WHENCE | 61 ++++++++++++++++++++++++++++++++++++- nvidia/gm200/acr/bl.bin | Bin 0 -> 832 bytes nvidia/gm200/acr/ucode_load.bin | Bin 0 -> 10144 bytes nvidia/gm200/acr/ucode_unload.bin | Bin 0 -> 1440 bytes nvidia/gm200/gr/fecs_bl.bin | Bin 0 -> 576 bytes nvidia/gm200/gr/fecs_data.bin | Bin 0 -> 1968 bytes nvidia/gm200/gr/fecs_inst.bin | Bin 0 -> 16271 bytes nvidia/gm200/gr/fecs_sig.bin | Bin 0 -> 76 bytes nvidia/gm200/gr/gpccs...

...--------------------------------- Alexandre Courbot (1): nvidia: Add GP100 signed firmware WHENCE | 15 +++++++++++++++ nvidia/gp100/acr/bl.bin | Bin 0 -> 832 bytes nvidia/gp100/acr/ucode_load.bin | Bin 0 -> 9632 bytes nvidia/gp100/acr/ucode_unload.bin | Bin 0 -> 1440 bytes nvidia/gp100/gr/fecs_bl.bin | 1 + nvidia/gp100/gr/fecs_data.bin | Bin 0 -> 2028 bytes nvidia/gp100/gr/fecs_inst.bin | Bin 0 -> 20955 bytes nvidia/gp100/gr/fecs_sig.bin | Bin 0 -> 76 bytes nvidia/gp100/gr/gpccs_bl.bin |...

...04/gr/fecs_data.bin nvidia/gp104/gr/fecs_sig.bin nvidia/gp104/gr/gpccs_bl.bin nvidia/gp104/gr/gpccs_inst.bin nvidia/gp104/gr/gpccs_data.bin nvidia/gp104/gr/gpccs_sig.bin nvidia/gp104/sec2/image.bin nvidia/gp104/sec2/desc.bin nvidia/gp104/sec2/sig.bin nvidia/gp104/acr/ucode_load.bin nvidia/gp104/acr/ucode_unload.bin nvidia/gp104/acr/bl.bin nvidia/gp104/acr/unload_bl.bin nvidia/gp104/nvdec/scrubber.bin" > > Bisecting is kinda painful with miscompilation and init/main.c breakage. > > > > BTW do I need all those megabytes of firmware? > > > > [ 0.923273] fb0: switching t...

This series fixes two cases where behavior on secure boot errors could be improved: 1) Patch 2 propages secure-boot errors from GR init, making sure initialization fails as it should. Failure to do so results in a black screen during boot, as reported in FD bug 94990. 2) Patches 3-4 make the absence of required secure firmware files a non-fatal error. The previous behavior was to give up

gp104 refuses to switch to "graphic" mode and show anything past this line: fb0: switching to nouveaufb from EFI VGA Machine is fine, as it I can press Ctrl+Alt+Delete and reboot it normally. 5.5 is OK. 5.6 is broken. Bisecting is kinda painful with miscompilation and init/main.c breakage. BTW do I need all those megabytes of firmware? [ 0.923273] fb0: switching to nouveaufb

...t_prepare_blobs(struct nvkm_secboot *sb) +{ + struct gm200_secboot *gsb = gm200_secboot(sb); + int ret; + + ret = gm20x_secboot_prepare_blobs(gsb); + if (ret) + return ret; + + /* dGPU only: load the HS firmware that unprotects the WPR region */ + ret = gm200_secboot_prepare_hs_blob(gsb, "acr/ucode_unload", + &gsb->acr_unload_blob, + &gsb->acr_unload_bl_desc, false); + if (ret) + return ret; + + return 0; +} + + + +/* + * Secure Boot Execution + */ + +/** + * gm200_secboot_load_hs_bl() - load HS bootloader into DMEM and IMEM + */ +static void +gm200_secboot_load_h...

Hi everyone, Apologies for the big patchset. This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send

https://bugs.freedesktop.org/show_bug.cgi?id=100567 Bug ID: 100567 Summary: Nouveau system freeze fifo: SCHED_ERROR 0a [CTXSW_TIMEOUT] Product: xorg Version: unspecified Hardware: Other OS: All Status: NEW Severity: normal Priority: medium Component: Driver/nouveau

...t;acr_load_blob, - &gsb->acr_load_bl_desc, true); + &gsb->load_bl_header, true); if (ret) return ret; } @@ -965,7 +963,7 @@ gm200_secboot_prepare_blobs(struct gm200_secboot *gsb) if (!gsb->acr_unload_blob) { ret = gm200_secboot_prepare_hs_blob(gsb, "acr/ucode_unload", &gsb->acr_unload_blob, - &gsb->acr_unload_bl_desc, false); + &gsb->unload_bl_header, false); if (ret) return ret; } @@ -1086,35 +1084,37 @@ gm200_secboot_setup_falcon(struct gm200_secboot *gsb) * gm200_secboot_run_hs_blob() -...

New version of the secure boot code that works with the blobs just merged into linux-firmware. Since the required Mesa patches are also merged, this set is the last piece of the puzzle to get out-of-the-box accelerated Maxwell 2. The basic code remains the same, with a few improvements with respect to how secure falcons are started. Hopefully the patchset is better split too. I have a

https://bugs.freedesktop.org/show_bug.cgi?id=101887 Bug ID: 101887 Summary: gtx 970 black screen Product: xorg Version: unspecified Hardware: x86-64 (AMD64) OS: Linux (All) Status: NEW Severity: normal Priority: medium Component: Driver/nouveau Assignee: nouveau at

Sending things in a smaller chunks since it makes their reviewing easier. This part part 2/3 of the secboot refactoring/PMU command support patch series. Part 1 was the new falcon library which should be merged soon now. This series is mainly a refactoring/sanitization of the existing secure boot code. It does not add new features (part 3 will). Secure boot handling is now separated by NVIDIA

This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send the code to manage then, but hopefully the

This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send the code to manage then, but hopefully the

This revision includes initial signed PMU firmware support for GM20B (Tegra X1). This PMU code will also be used as a basis for dGPU signed PMU firmware support. With the PMU code, the refactoring of secure boot should also make more sense. ACR (secure boot) support is now separated by the driver version it originates from. This separation allows to run any version of the ACR on any chip,