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https://bugzilla.samba.org/show_bug.cgi?id=12508 Bug ID: 12508 Summary: fileflags & forcechange don't work for hardlinks Product: rsync Version: 3.1.2 Hardware: All OS: FreeBSD Status: NEW Severity: normal Priority: P5 Component: core Assignee: wayned at samba.org

Hello, Thanks for the advice. I have looked for the libs and here is the difference: Dovecot production env 2.2.10: /usr/lib/dovecot/modules/doveadm rw-r--r-- 1 root root 18560 Jan 9 2014 lib10_doveadm_acl_plugin.so -rw-r--r-- 1 root root 14256 Jan 9 2014 lib10_doveadm_expire_plugin.so -rw-r--r-- 1 root root 10232 Jan 9 2014 lib10_doveadm_quota_plugin.so -rw-r--r-- 1 root root

Hi all, I'm primarily a hardware person but would like to do some compiler-architecture co-design research. Are there any good references for the NVPTX backend? I'd like to change that backend to have a limited number of physical registers rather than an unlimited number of virtual ones (for more realistic modeling in a uarch simulator). Being able to do register allocation and other

Greg Rivers <gcr+dovecot at tharned.org> wrote: > On Saturday, May 09, 2015 22:25:48 Michael Grimm wrote: >>> or just try if it works if you change it to /bin/sh and use whatever >>> FreeBSD has that pointing to. >> That fails because /bin/sh equals /bin/csh at FBSD. > I don't know if it fails or not, but if it does this is not the reason. > /bin/sh

On Thursday 23 July 2009 18:07, Evan Cheng wrote: > Ok. As with any heuristics change, some tests will benefit, some will > suffer. I am ok with both sets of changes assuming there are ways to > control them. Yep, we have flags. > Post-ra scheduling has been working for a while. The reason it's not > turned on for x86 is it's not helping much (1 or 2%) while the compile

On Fri, Jun 26, 2015 at 2:17 PM, Joerg Sonnenberger <joerg at britannica.bec.de > wrote: > On Fri, Jun 26, 2015 at 12:51:38PM -0600, Sanjay Patel wrote: > > Assuming the transform is correct, what is the recommended way to write > > this in C/C++ to achieve the desired effect: we want both comparisons to > be > > evaluated (do *not* want short-circuiting)? > >

> From: fglaser at apple.com <fglaser at apple.com> On Behalf Of escha at apple.com > Sent: Saturday, April 7, 2018 8:22 AM > >> I realize this is a micro-op saving a single cycle.  But this reduces the instruction count, one less >> instr to decode in a potentially hot path. If this all makes sense, and seems like a reasonable addition >> to llvm, would it make

On Jul 23, 2009, at 12:42 PM, David Greene wrote: > We have two features for register allocation we'd like to contribute > if folks > think they are worthwhile. We want to get a read on whether they > will be > useful to people. > > The first features backschedules reloads during the spilling phase. > As > reloads are generated, we have some very simple code

Hi ? Teemu Huovila <teemu.huovila at dovecot.fi> wrote: > On 04/24/2015 10:00 PM, Michael Grimm wrote: >> 1) I'm trying to compile a recent hg dovecot version (008632bdfd2c) at a FBSD10-STABLE system without success: [?] >> fts-tokenizer-generic.c:214:18: error: use of undeclared identifier 'MidNum' >> if (uint32_find(MidNum, N_ELEMENTS(MidNum), c,

On Mon, Feb 13, 2017 at 2:06 PM Gerolf Hoflehner via llvm-dev < llvm-dev at lists.llvm.org> wrote: > For unrolling specifically I agree with Hal that the hooks should be > target specific. Actually, I go further and think they should be uArch > specific. > They already are, it is just that no one has contributed a patch to use this on x86 microarchitectures. Until someone

On Oct 26, 2013, at 5:02 PM, Chris Lattner <clattner at apple.com> wrote: > On Oct 25, 2013, at 5:22 PM, Sean Silva <chisophugis at gmail.com> wrote: >> I’m not sure macros are a good analogy, but there are other pseudo-instructions that we’re not always able to reconstruct in disassembled code back to how the user wrote them. Or if we do, it’s purely via heuristic methods. I

On Oct 25, 2013, at 5:22 PM, Sean Silva <chisophugis at gmail.com> wrote: > I’m not sure macros are a good analogy, but there are other pseudo-instructions that we’re not always able to reconstruct in disassembled code back to how the user wrote them. Or if we do, it’s purely via heuristic methods. I don’t see this as a big issue. I agree. These pseudo instructions seem like pure

On Fri, Oct 25, 2013 at 7:30 PM, Jim Grosbach <grosbach at apple.com> wrote: > > On Oct 25, 2013, at 3:53 PM, David Peixotto <dpeixott at codeaurora.org> > wrote: > > Hi Renato, Thanks for the thoughtful reply. Please find my thoughts below. > **** > > -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, > hosted by The Linux Foundation****

(As per IRC discussion) I understand that the carry-less multiplication algorithm has it's uses since/and it is implemented as an instruction in many architectures and that adding it as a general-purpose intrinsic will allow us to drop target-specific intrinsics as by-product. What i do *NOT* understand is: what is the actual/main goal/driving factor of adding an LLVM intrinsic for it? The

We have two features for register allocation we'd like to contribute if folks think they are worthwhile. We want to get a read on whether they will be useful to people. The first features backschedules reloads during the spilling phase. As reloads are generated, we have some very simple code to try to schedule them as far ahead of the use as possible. The second features modifies

On Tue, Oct 29, 2013 at 1:21 PM, Jim Grosbach <grosbach at apple.com> wrote: > > On Oct 26, 2013, at 5:02 PM, Chris Lattner <clattner at apple.com> wrote: > > On Oct 25, 2013, at 5:22 PM, Sean Silva <chisophugis at gmail.com> wrote: > > I’m not sure macros are a good analogy, but there are other >> pseudo-instructions that we’re not always able to

----- Original Message ----- > From: "Chandler Carruth" <chandlerc at google.com> > To: "Sanjay Patel" <spatel at rotateright.com>, "Clang" <cfe-dev at cs.uiuc.edu>, llvmdev at cs.uiuc.edu, > joerg at britannica.bec.de > Sent: Friday, June 26, 2015 8:55:22 PM > Subject: Re: [LLVMdev] [cfe-dev] bitwise ops on booleans > > >

On 29 February 2012 09:35, Chandler Carruth <chandlerc at google.com> wrote: > I still think we can do more, but it's already much faster than the existing LLVM one except for the issue Tobias pointed out w/ modulo-4 key sizes. I'm going to investigate this OK, but this is a VERY big exception! Almost any non-string data anyone wants to hash will be a multiple of 4 bytes in

http://llvm.org/docs/CodeGenerator.html#machine-code-description-classes Section starting: Fixed (preassigned) registers It talks about converting: define i32 @test(i32 %X, i32 %Y) { %Z = udiv i32 %X, %Y ret i32 %Z } into ;; X is in EAX, Y is in ECX mov %EAX, %EDX sar %EDX, 31 idiv %ECX ret BUT, where does the "sar" come from? Kind Regards James

WARNING: This is not compatible with the previous lz4 patchset. If you''re using experimental compression that isn''t in mainline kernels, be prepared to backup and restore or decompress before upgrading, and have backups in case it eats data (which appears not to be a problem any more, but has been during development). These patches add lz4 and lz4hc compression