Displaying 1 result from an estimated 1 matches for "uaddv".
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2016 Nov 04
2
[RFC] Supporting ARM's SVE in LLVM
...;; Control 3
%12 = test first true <n x 4 x i1> %predicate.next ;; Control 4
br i1 %12, label %vector.body, label %middle.block, !llvm.loop !5
middle.block:
%.lcssa = phi <n x 4 x i32> [ %8, %vector.body ]
%13 = call i64 @llvm.aarch64.sve.uaddv.nxv4i32(<n x 4 x i1> shufflevector
(<n x 4 x i1> insertelement (<n x 4 x i1> undef, i1 true, i32 0),
<n x 4 x i1> undef, <n x 4 x i32> zeroinitializer), <n x 4 x i32> %.lcssa)
%14 = trunc i64 %13 to i32
br label %for.cond.cleanup
for....