Displaying 5 results from an estimated 5 matches for "uadd_with_overflow".
2019 Jul 03
3
optimisation issue in an llvm IR pass
...antInt::get(Int8Ty, 1));
auto carry = IRB.CreateZExt(cf, Int8Ty);
Incr = IRB.CreateAdd(Incr, carry);
it makes no difference to the generated assembly
> Have you tried using the llvm.uadd.with.overflow.i8 intrinsic?
we have tried this:
CallInst *AddOv =
IRB.CreateBinaryIntrinsic(Intrinsic::uadd_with_overflow, Counter,
ConstantInt::get(Int8Ty, 1));
AddOv->setMetadata(M.getMDKindID("nosanitize"), MDNode::get(C, None));
Value *SumWithOverflowBit = AddOv;
Incr = IRB.CreateAdd(IRB.CreateExtractValue(SumWithOverflowBit, 0),
IRB.CreateZExt(IRB.CreateExtractValue(SumWithOverflowBit, 1), Int8Ty...
2013 Apr 25
0
[LLVMdev] Proposal for new Legalization framework
...9;m ok with rewriting it in MachineInstrs if
> that's the consensus.
>
> Given that the code I wrote operates on LLVM IR, it raises the following
> interesting issues:
>
> The code I wrote in the attached patch operates on LLVM IR, so for
> example it expands adds into llvm.uadd_with_overflow intrinsics. The
> intrinsics available in LLVM IR today aren't as expressive as the ISD
> operator set in SelectionDAG, so the generated code is quite a bit more
> verbose in some cases. Should we instead add new intrinsics, for add and
> for a bunch of other things? People I've...
2013 Apr 25
11
[LLVMdev] Proposal for new Legalization framework
...to develop
it this way, but I'm ok with rewriting it in MachineInstrs if that's the
consensus.
Given that the code I wrote operates on LLVM IR, it raises the following
interesting issues:
The code I wrote in the attached patch operates on LLVM IR, so for example
it expands adds into llvm.uadd_with_overflow intrinsics. The intrinsics
available in LLVM IR today aren't as expressive as the ISD operator set in
SelectionDAG, so the generated code is quite a bit more verbose in some
cases. Should we instead add new intrinsics, for add and for a bunch of
other things? People I've talked to so far we...
2013 Apr 25
0
[LLVMdev] Proposal for new Legalization framework
...way, but I'm ok with rewriting it in MachineInstrs if that's the consensus.
>
> Given that the code I wrote operates on LLVM IR, it raises the following interesting issues:
>
> The code I wrote in the attached patch operates on LLVM IR, so for example it expands adds into llvm.uadd_with_overflow intrinsics. The intrinsics available in LLVM IR today aren't as expressive as the ISD operator set in SelectionDAG, so the generated code is quite a bit more verbose in some cases. Should we instead add new intrinsics, for add and for a bunch of other things? People I've talked to so far we...
2019 Jul 03
2
optimisation issue in an llvm IR pass
Hello,
I have an optimisation issue in an llvm IR pass - the issue being that
unnecessary instructions are generated in the final assembly (with -O3).
I want to create the following assembly snippet:
mov dl,BYTE PTR [rsi+rdi*1]
add dl,0x1
adc dl,0x0
mov BYTE PTR [rsi+rdi*1],dl
however what is created is (variant #1):
mov dl,BYTE PTR [rsi+rdx*1]
add dl,0x1
cmp