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The BGL (Boost Graph Library) defines tie(), which is exactly what the tie() defined in STLExtras.h. The header files of GBL use boost::tie(), and other boost libraries use boost::tie() too. How to resolve the ambiguity for compiler? -- Tzu-Chien Chiu, 3D Graphics Hardware Architect <URL:http://www.csie.nctu.edu.tw/~jwchiu>

On 9/22/05, Tzu-Chien Chiu <tzuchien.chiu at gmail.com> wrote: > The BGL (Boost Graph Library) defines tie(), which is exactly what the > tie() defined in STLExtras.h. > > The header files of GBL use boost::tie(), and other boost libraries > use boost::tie() too. > > How to resolve the ambiguity for compiler? &...

Can the driver (llvmc) be built on win32?

%foo1 = constant <4 x float> <float 1.0, float 2.0, float 3.0, float 4.0>; void %main() { %x = mul <4 x float> %foo1, %foo1 ret void } llvm-as complained " Reference to an invalid definition: 'foo1' of type '<4 x float>' ". I searched all test script in llvm/test, and I found the only way to use packed constant is: %foo1 = uninitialized

http://llvm.cs.uiuc.edu/docs/CodeGenerator.html "A SelectionDAG has designated "Entry" and "Root" nodes. The Entry node is always a marker node with an Opcode of ISD::TokenFactor. The Root node is the final side-effecting node in the token chain. For example, in a single basic block function, this would be the return node." Isn't it should be: "...The

national compiler infrastructure - http://www.cs.virginia.edu/nci/ is there any on-going efforts to integrate llvm with other nci projects?

i don't know the status of nci, but suif/suif2 development and publication is very active. it's will be great if there are tools to transform llvm ir and suif ir to each other. acutally, i didn't use suif but llvm just because suif cannot be compiled by visual studio.net (but visual studio 6). On 5/10/05, Vladimir Prus <ghost at cs.msu.su> wrote: > On Tuesday 10 May 2005

i want to extend a burg-style code generator generator to write a retargetable compiler, implementing the algorithm: Rainer Leupers: Code Selection for Media Processors with SIMD Instructions. DATE 2000: 4-8 what i have now is only iburg, though robust but with very limited functionality. i have consider using "nova" - http://cocom.sourceforge.net/nona.html but it seems not be

2005/7/24, Chris Lattner <sabre at nondot.org>: > Ah, ok. In that case, you want to put all of the registers in one register > file, and not make the constant register allocatable (e.g. see > X86RegisterInfo.td, and note how the register classes include EBP and ESP, > but do not register allocate them (through the definition of > allocation_order_end()). > > -Chris

LegalizeDAG.cpp SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { case ISD::RET: Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. switch (Node->getNumOperands()) { case 2: // ret val [skipped] case 1: // ret void [skipped] default: { // ret <values> [skipped] Does it imply that a ret instruction may

How to define a MachineFunctionPass requireing one of the register allocation passes being executed first? Should there be a PassInfo for register allocation in Pass.h? Pass.h: namespace llvm { extern const PassInfo *PHIEliminationID; extern const PassInfo *TwoAddressInstructionPassID; extern const PassInfo *RegisterAllocationPassID; // <-- add this one? There are four

I want to enumerate all the operands of a machine instruction, but the iterator seems to skip everything except virtual registers. Is this by design? MachineInstr.h <code> template<class MITy, class VTy> class ValOpIterator : public forward_iterator<VTy, ptrdiff_t> { void skipToNextVal() { while (i < MI->getNumOperands() && !(

Yes, unfortunately I am using the Visual C++ .NET compiler. Morten Ofstad wrote: > This problem is the motivation for having the _X86TargetMachineModule > symbol in LLVM. I thought this problem was solved by explictly list the object files in the "Additional Dependencies" of the project file? win32/llc/llc.vcproj:

On 08/09/05, Chris Lattner <sabre at nondot.org> wrote: > This code isn't actually replacing the virtual register with a physreg. Then why changing its optype? It makes the assertion fails: MachineOperand& MO = inst.getOperand(n); if (MRegisterInfo::isVirtualRegister(MO.getReg())) { assert(MachineOperand::MO_VirtualRegister == MO.getType()); ... } Is that alright? Some

On 08/09/05, Alkis Evlogimenos <evlogimenos at gmail.com> wrote: > to those coalesced registers, it is logical that noone will ever query > the liveness of those registers (unless there is a bug somewhere in the Indeed the coalesced registers may logically not be queried since they do not appear in any operand list of the machine code, but the VarInfo::DefInst in VirtRegInfo of the

On 08/09/05, Alkis Evlogimenos <evlogimenos at gmail.com> wrote: > representative register (found using a union find algorithm). Note that > the representative register could be a real register if we ever joined > an interval of a real register with one of a virtual register (and this > real register will be the representative register of the set of > intervals joined

http://llvm.cs.uiuc.edu/~gaeke/llvm-tv File Not Found? -- Tzu-Chien Chiu, 3D Graphics Hardware Architect <URL:http://www.csie.nctu.edu.tw/~jwchiu>

The automated tests seems not run periodically. Some builds are even broken (http://llvm.cs.uiuc.edu/testresults/X86-niobe/), and some failed (http://llvm.cs.uiuc.edu/testresults/SparcV9/). Will there be another automated test be scheduled before the next release? On 11/10/05, Bill Wendling <isanbard at gmail.com> wrote: > Frequently releasing software can be a good thing. Especially

2005/12/13, Chris Lattner <sabre at nondot.org>: > > For example, this a code snippet for the file generated by the TableGen tool: > ... > > Somewhere in my code, I have to write: > > unsigned opcode = MI->getOpcode(); // MachineInstr* > > if (CMPfaaaa == opcode || > > CMPfaaar == opcode || > > CMPfaara == opcode || > > ...

LiveInterval.cpp. // that v is live at i'. In this implementation intervals can have holes, // i.e. an interval might look like [1,20), [50,65), [1000,1001). Each // individual range is represented as an instance of LiveRange, and the whole // interval is represented as an instance of LiveInterval. What cause these holes? -- Tzu-Chien Chiu - XGI Technology, Inc. URL: