Displaying 6 results from an estimated 6 matches for "type_s8".
2016 Sep 27
2
[PATCH] nv50/ir: constant fold OP_SPLIT
...if (i->sType == TYPE_U32 || i->sType == TYPE_S32) {
+ shift = 16;
+ type = (i->sType == TYPE_U32) ? TYPE_U16 : TYPE_S16;
+ }
+ if (i->sType == TYPE_U16 || i->sType == TYPE_S16) {
+ shift = 8;
+ type = (i->sType == TYPE_U16) ? TYPE_U8 : TYPE_S8;
+ }
+ if (type != TYPE_NONE) {
+ bld.mkMov(i->getDef(0), bld.mkImm(imm0.reg.data.u64 >> shift), type);
+ bld.mkMov(i->getDef(1), bld.mkImm(imm0.reg.data.u64), type);
+ delete_Instruction(prog, i);
+ }
+ }
+ break;
case OP_MUL:
if (i...
2016 Sep 30
2
[PATCH] nv50/ir: constant fold OP_SPLIT
..._S32) {
>> + shift = 16;
>> + type = (i->sType == TYPE_U32) ? TYPE_U16 : TYPE_S16;
>> + }
>> + if (i->sType == TYPE_U16 || i->sType == TYPE_S16) {
>> + shift = 8;
>> + type = (i->sType == TYPE_U16) ? TYPE_U8 : TYPE_S8;
>> + }
> shift = typeSizeOf(i->dType);
>
>> + if (type != TYPE_NONE) {
>> + bld.mkMov(i->getDef(0), bld.mkImm(imm0.reg.data.u64 >> shift), type);
>> + bld.mkMov(i->getDef(1), bld.mkImm(imm0.reg.data.u64), type);
> u64 val =...
2016 Sep 28
0
[PATCH] nv50/ir: constant fold OP_SPLIT
...2 || i->sType == TYPE_S32) {
> + shift = 16;
> + type = (i->sType == TYPE_U32) ? TYPE_U16 : TYPE_S16;
> + }
> + if (i->sType == TYPE_U16 || i->sType == TYPE_S16) {
> + shift = 8;
> + type = (i->sType == TYPE_U16) ? TYPE_U8 : TYPE_S8;
> + }
shift = typeSizeOf(i->dType);
> + if (type != TYPE_NONE) {
> + bld.mkMov(i->getDef(0), bld.mkImm(imm0.reg.data.u64 >> shift), type);
> + bld.mkMov(i->getDef(1), bld.mkImm(imm0.reg.data.u64), type);
u64 val = ...u64;
for (d = 0; i->de...
2016 Sep 30
0
[PATCH] nv50/ir: constant fold OP_SPLIT
...shift = 16;
>>> + type = (i->sType == TYPE_U32) ? TYPE_U16 : TYPE_S16;
>>> + }
>>> + if (i->sType == TYPE_U16 || i->sType == TYPE_S16) {
>>> + shift = 8;
>>> + type = (i->sType == TYPE_U16) ? TYPE_U8 : TYPE_S8;
>>> + }
>>
>> shift = typeSizeOf(i->dType);
>>
>>> + if (type != TYPE_NONE) {
>>> + bld.mkMov(i->getDef(0), bld.mkImm(imm0.reg.data.u64 >> shift),
>>> type);
>>> + bld.mkMov(i->getDef(1), bld.mk...
2015 Nov 05
7
[PATCH mesa 0/5] nouveau: codegen: Make use of double immediates
Hi All,
This series implements using double immediates in the nouveau codegen code.
This turns the following (nvc0) code:
1: mov u32 $r2 0x00000000 (8)
2: mov u32 $r3 0x3fe00000 (8)
3: add f64 $r0d $r0d $r2d (8)
Into:
1: add f64 $r0d $r0d 0.500000 (8)
This has been tested with the 2 double shader tests which I just send to
the piglet list. On a gk208 (gk110 / SM35)
2015 Aug 19
5
[PATCH 1/2] nvc0/ir: detect AND/SHR pairs and convert into EXTBF
Some shaders appear to extract bits using shift/and combos. Detect
(some) of those and convert to EXTBF instead.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
.../drivers/nouveau/codegen/nv50_ir_peephole.cpp | 66 +++++++++++++++-------
1 file changed, 46 insertions(+), 20 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp