search for: type_nr

...*intspec, unsigned int intsize, return 0; } + +static void do_dump_gic(unsigned char key) +{ + int irq; + printk("''%c'' pressed -> dumping GIC state\n", key); + + for ( irq = 0; irq < gic.lines; irq++ ) + { + const char *type; + int type_nr, enable, pend, active, priority, target; + struct irq_desc *desc = irq_to_desc(irq); + uint8_t *bytereg; + uint32_t wordreg; + + bytereg = (uint8_t *) (GICD + GICD_ITARGETSR); + target = bytereg[irq]; + + bytereg = (uint8_t *) (GICD + GICD_IPRIORITYR); +...

I''m afraid this series is rather a grab bag and it is distressingly large at this stage. With this series I can boot an Xgene board until it fails to find its SATA controller. This is a dom0 issue for which patches are pending from APM (/me nudges Anup). As well as the APM specific platform stuff there are also some generic improvements which were either necessary or useful during this

...t a/drivers/gpu/drm/nouveau/include/nvif/mmu.h b/drivers/gpu/drm/nouveau/include/nvif/mmu.h index 747ecf67e403..cec1e88a0a05 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/mmu.h +++ b/drivers/gpu/drm/nouveau/include/nvif/mmu.h @@ -7,6 +7,7 @@ struct nvif_mmu { u8 dmabits; u8 heap_nr; u8 type_nr; + u8 kind_inv; u16 kind_nr; s32 mem; @@ -36,9 +37,8 @@ void nvif_mmu_fini(struct nvif_mmu *); static inline bool nvif_mmu_kind_valid(struct nvif_mmu *mmu, u8 kind) { - const u8 invalid = mmu->kind_nr - 1; if (kind) { - if (kind >= mmu->kind_nr || mmu->kind[kind] == invalid...