Displaying 5 results from an estimated 5 matches for "type09".
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type00
2017 Apr 10
0
[PATCH 04/11] nvkm/ramgt215: Move ram training up the chain
...**);
+/* Training */
+struct gt215_ram_train {
+ u16 mask;
+ struct nvbios_M0209S remap;
+ struct nvbios_M0209S type00;
+ struct nvbios_M0209S type01;
+ struct nvbios_M0209S type04;
+ struct nvbios_M0209S type06;
+ struct nvbios_M0209S type07;
+ struct nvbios_M0209S type08;
+ struct nvbios_M0209S type09;
+};
+int gt215_ram_train_type(struct nvkm_ram *ram, int i, u8 ramcfg,
+ struct gt215_ram_train *train);
+int gf100_ram_train_init(struct nvkm_ram *ram);
+
int gk104_ram_ctor(struct nvkm_fb *, struct nvkm_ram **, u32);
int gk104_ram_init(struct nvkm_ram *ram);
diff --git a/drivers/gpu/...
2017 Apr 10
0
[PATCH 07/11] nvkm/ramgf100: Reinstate default ram train pattern
...j, 0x00000000 | (i << 8));
- nvkm_wr32(device, 0x10f920 + j, 0x00000000 |
- train->type08.data[i] << 4 |
- train->type06.data[i]);
- nvkm_wr32(device, 0x10f918 + j, train->type00.data[i]);
- nvkm_wr32(device, 0x10f920 + j, 0x00000100 |
- train->type09.data[i] << 4 |
- train->type07.data[i]);
- nvkm_wr32(device, 0x10f918 + j, train->type01.data[i]);
+ static const u8 train0[] = {
+ 0x00, 0xff, 0x55, 0xaa, 0x33, 0xcc,
+ 0x00, 0xff, 0xff, 0x00, 0xff, 0x00,
+ };
+
+ static const u32 train1[] = {
+ 0x00000000, 0xffffffff,
+...
2017 Apr 10
11
Preparations for Fermi DRAM clock changes
No, no, these will not implement Fermi reclocking. This set of patches
contains some of the preparatory work that I deem stable enough to
move upstream. Notable changes
- Training pattern upload routines from GK104+ now shared with GT215+
- Timing calculation for Fermi
- GDDR5 MR calculation from VBIOS timing table v1.0. Also useful for that
pesky GT 240.
- A routine to translate a VBIOS init
2017 Apr 10
14
RESEND Preparations for Fermi DRAM clock changes
Two patches went missing as a result of PEBCAK. No v2 marks as nothing
changed really. Just resending for easier enforcement of patch order
in other people's trees. Sorry for the noise.
Original message:
No, no, these will not implement Fermi reclocking. This set of patches
contains some of the preparatory work that I deem stable enough to
move upstream. Notable changes
- Training pattern
2017 Apr 10
0
[PATCH 08/11] nvkm/ramgt215: Add train ptrn upload for GDDR5
...f (i < 0x30) {
+ nvkm_wr32(device, 0x10f940 + off[j], 0x00000000 |
+ train->type08.data[i] << 4 |
+ train->type06.data[i]);
+ nvkm_wr32(device, 0x10f900 + off[j],
+ train->type00.data[i]);
+ nvkm_wr32(device, 0x10f940 + off[j], 0x00000100 |
+ train->type09.data[i] << 4 |
+ train->type07.data[i]);
+ nvkm_wr32(device, 0x10f900 + off[j],
+ train->type01.data[i]);
+ }
+ nvkm_wr32(device, 0x10f840 + off[j], 0x00000000 | i);
+ nvkm_wr32(device, 0x10f840 + off[j], 0x01000000 | i);
+ }
+ }
+
+ return 0;
+}
+
+static int
+gt215...