search for: twoaddressinstruction

...propagates immediates rather than registers. For example, I want to transform: ... %vreg1 = V_MOV_B32 1 %vreg2 = V_ADD_I32 %vreg1, %vreg0 ... into: %vreg1 = V_MOV_B32 1 ; <- Only delete this if it is dead %vreg2 = V_ADD_I32 1, %vreg0 For best results, I am trying to run this pass after the TwoAddressInstruction pass, which means I need to preserve the LiveIntervals analysis. My question is: How do I update the LiveIntervals to reflect the fact that V_ADD_I32 no longer uses %vreg0? Thanks, Tom

Hi, We recently found a testcase showing that simplifications in instcombine sometimes change the instruction without reducing the instruction cost, but causing problems in TwoAddressInstruction pass. And it looks like the problem is generic and other simplification may have the same issue. I want to get some ideas about what is the best way to fix such kind of problem. The testcase: ----------------------------- a.ll ---------------------------------- @a = global i64 0, align 8 @b = glob...

So what is the status about LiveVariables. Is there a plan to remove it? After searching in old lvm-dev-mails it is mentioned that LiveVariable still exists due to one pass needing it. And a comment in TargetPassConfig.cpp indicates that the pass in question is TwoAddressInstruction: // FIXME: Once TwoAddressInstruction pass no longer uses kill flags, // LiveVariables can be removed completely, and LiveIntervals can be directly // computed. (We still either need to regenerate kill flags after regalloc, or // preferably fix the scavenger to not depend on them). When...

...3:00 PM, Wei Mi via llvm-dev <llvm-dev at lists.llvm.org> wrote: >> >> Hi, >> >> We recently found a testcase showing that simplifications in >> instcombine sometimes change the instruction without reducing the >> instruction cost, but causing problems in TwoAddressInstruction pass. >> And it looks like the problem is generic and other simplification may >> have the same issue. I want to get some ideas about what is the best >> way to fix such kind of problem. >> >> The testcase: >> ----------------------------- a.ll ------------------...

...-stack-protector -preverify -domtree -verify -loops -branch-prob -expand-isel-pseudos -tailduplication -opt-phis -localstackalloc -dead-mi-elimination -machinedomtree -machine-loops -machinelicm -machine-cse -machine-sink -peephole-opts -unreachable-mbb-elimination -livevars -phi-node-elimination -twoaddressinstruction -processimpdefs -slotindexes -liveintervals -livedebugvars -simple-register-coalescing -calcspillweights -livestacks -virtregmap -edge-bundles -spill-code-placement -stack-slot-coloring -machinelicm -edge-bundles -prologepilog -branch-folder -tailduplication -machine-cp -postrapseudos -machinedomtr...

On Dec 7, 2007, at 1:43 AM, Wojciech Matyjewicz wrote: > Recently, I was looking into the bug #1227. I wanted to check if > reordering optimization passes could solve it. To start with, I > tried to > reproduce the output of llvm-g++ -O3 using the combination of llvm-g++ > -O0 and opt with the appropriate passes. However, I was unable to. I > use > SVN versions of llvm and

...ination -machinedomtree -machine-loops -machine-trace-metrics -early-ifcvt -machinelicm -machine-cse -machinepostdomtree -machine-block-freq -machine-sink -peephole-opts -dead-mi-elimination -processimpdefs -unreachable-mbb-elimination -livevars -machinedomtree -machine-loops -phi-node-elimination -twoaddressinstruction -slotindexes -liveintervals -simple-register-coalescing -misched -machine-block-freq -livedebugvars -livestacks -virtregmap -liveregmatrix -edge-bundles -spill-code-placement -virtregrewriter -stack-slot-coloring -machinelicm -edge-bundles -prologepilog -machine-block-freq -branch-folder -taildupli...

Where is the liveness analysis pass? I have been looking for days but cannot find anything. I just want to know transfer variables in and out of basic blocks, that are calculated using simple data flow equations. Thanks! -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20180920/529bce15/attachment.html>

Hello to all LLVM Developers. The LLVM IR is in strict SSA form (i.e. every variable is defined before it is used along every path from the entry to exit point)? According to the documentation, currently the LLVM IR is in the SSA form, but I don't see additional information about *strict* SSA form. The strict SSA form provide opportunities of optimization in register allocation, because is

Hi Susan, The meaning of "addRequired(X)" is that your pass needs X to be run, and for X to be preserved by all passes that run after X and before your pass. The PHIElemination and TwoAddressInstruction passes do not preserve each other, hence there's no way for the pass manager to schedule them for you if you addRequire(...) them. The trick is that CodeGen will schedule both of these passes to be run before _any_ register allocation pass (see Passes.cpp), so you needn't require them expl...

...ify > -domtree -verify -loops -branch-prob -expand-isel-pseudos > -tailduplication -opt-phis -localstackalloc -dead-mi-elimination > -machinedomtree -machine-loops -machinelicm -machine-cse -machine-sink > -peephole-opts -unreachable-mbb-elimination -livevars > -phi-node-elimination -twoaddressinstruction -processimpdefs > -slotindexes -liveintervals -livedebugvars -simple-register-coalescing > -calcspillweights -livestacks -virtregmap -edge-bundles > -spill-code-placement -stack-slot-coloring -machinelicm -edge-bundles > -prologepilog -branch-folder -tailduplication -machine-cp > -po...

Hi, Recently, I was looking into the bug #1227. I wanted to check if reordering optimization passes could solve it. To start with, I tried to reproduce the output of llvm-g++ -O3 using the combination of llvm-g++ -O0 and opt with the appropriate passes. However, I was unable to. I use SVN versions of llvm and llvm-gcc-4.2. First, I compile example.cpp (attached; taken from the bug #1227) with: $

...ou help with this? Thanks again! Susan On 10/31/2012 04:55 PM, Lang Hames wrote: > Hi Susan, > > The meaning of "addRequired(X)" is that your pass needs X to be run, and > for X to be preserved by all passes that run after X and before your > pass. The PHIElemination and TwoAddressInstruction passes do not > preserve each other, hence there's no way for the pass manager to > schedule them for you if you addRequire(...) them. > > The trick is that CodeGen will schedule both of these passes to be run > before _any_ register allocation pass (see Passes.cpp), so you needn...

I'm trying to write a MachineFunctionPass to do register allocation. I have code that worked with an old version of LLVM. It does not work with llvm-3.1. (or various other versions that I've tried). The first problem is that including this line: AU.addRequiredID(TwoAddressInstructionPassID); in method getAnalysisUsage causes a runtime error: Unable to schedule 'Eliminate PHI nodes for register allocation' required by 'Unnamed pass: implement Pass::getPassName()' Unable to schedule pass UNREACHABLE executed at ... I'm invoking the pass like this (given in...

...On Aug 2, 2017, at 3:00 PM, Wei Mi via llvm-dev <llvm-dev at lists.llvm.org> > wrote: > > Hi, > > We recently found a testcase showing that simplifications in > instcombine sometimes change the instruction without reducing the > instruction cost, but causing problems in TwoAddressInstruction pass. > And it looks like the problem is generic and other simplification may > have the same issue. I want to get some ideas about what is the best > way to fix such kind of problem. > > The testcase: > ----------------------------- a.ll ---------------------------------- > @a...

...n > > > On 10/31/2012 04:55 PM, Lang Hames wrote: > >> Hi Susan, >> >> The meaning of "addRequired(X)" is that your pass needs X to be run, and >> for X to be preserved by all passes that run after X and before your >> pass. The PHIElemination and TwoAddressInstruction passes do not >> preserve each other, hence there's no way for the pass manager to >> schedule them for you if you addRequire(...) them. >> >> The trick is that CodeGen will schedule both of these passes to be run >> before _any_ register allocation pass (see Passe...

...erify -domtree -verify -loops -loopsimplify -scalar-evolution -iv-users -loop-reduce -lowerinvoke -unreachableblockelim -codegenprepare -stack-protector -machine-function-analysis -machinedomtree -machine-loops -machinelicm -machine-sink -unreachable-mbb-elimination -livevars -phi-node-elimination -twoaddressinstruction -liveintervals -simple-register-coalescing -livestacks -virtregmap -linearscan-regalloc -stack-slot-coloring -prologepilog -machinedomtree -machine-loops -machine-loops I'm sure I can hack away to manually add these passes, but I'd prefer an informed opinion on the best way to achieve this...

.../2012 04:55 PM, Lang Hames wrote: > > Hi Susan, > > The meaning of "addRequired(X)" is that your pass needs X to be > run, and > for X to be preserved by all passes that run after X and before your > pass. The PHIElemination and TwoAddressInstruction passes do not > preserve each other, hence there's no way for the pass manager to > schedule them for you if you addRequire(...) them. > > The trick is that CodeGen will schedule both of these passes to > be run > before _any_ register a...

...S is still required since the ADDSS alone would not be equivalent to the hardware 'movss' instruction. I then started investigating the possibility of adding a pass that runs at 'postRegAlloc' stage. Before RegAlloc it may not be safe to remove the redundant MOVSSrr because of the TwoAddressInstruction Pass; this may decide to commute the operands of the ADDSS/MULSS. It is possible to write a pass that scans through each basic block in a function looking for opportunities to fold instructions based on the following patterns: ////// B<def, tied1> = #NAME#SSrr B<kill, tied0>, A...

Hi, On 12/06/12 13:09, Abdul Wahid Memon wrote: > Thanks alot. How can we view those optimization which are enabled when we do > > llc -O3 comb.ll llc -O3 comb.ll -debug-pass=Arguments > > Are these the same as the ones produced by the following command line no, as I mentioned before they are of a completely different nature to the optimizations that opt does. Ciao, Duncan.