search for: twoaddress

...rk that begun with setting 'guessInstructionProperties = 0' in the SystemZ backend. We have found this to be useful, and discovered many instructions where the hasSideEffects flag was incorrectly set while it actually shouldn't. The attached patch and test case triggers an assert in TwoAddress.  (bin/llc ./tc_TwoAddr_crash.ll -mtriple=s390x-linux-gnu -mcpu=z13) The only change in the patch is to remove the side effects flag from one instruction: -  def RISBMux : RotateSelectRIEfPseudo<GRX32, GRX32>; +  let hasSideEffects = 0 in +    def RISBMux : RotateSelectRIEfPseudo<GRX32...

Dear guys, I need help fixing a little piece of code. I have a pass that I really want to execute after the TwoAddressinstructionPass. But if I write "AU.addRequiredID(TwoAddressInstructionPassID);" in my pass' getAnalysisUsage, I end up getting the infamous: PassManagerT.h:387: failed assertion `getAnalysisOrNullUp(P) && dynamic_cast<ImmutablePass*>(getAnalysisOrNullUp(P)) &&am...

...begun with setting 'guessInstructionProperties = 0' in the SystemZ backend. We have found this to be useful, and discovered many instructions where the hasSideEffects flag was incorrectly set while it actually shouldn't. > > The attached patch and test case triggers an assert in TwoAddress. (bin/llc ./tc_TwoAddr_crash.ll -mtriple=s390x-linux-gnu -mcpu=z13) > > The only change in the patch is to remove the side effects flag from one instruction: > > - def RISBMux : RotateSelectRIEfPseudo<GRX32, GRX32>; > + let hasSideEffects = 0 in > + def RISBMux : Rot...

Hi, I would like to access the AsmPrinter MachineFunctionPass during compilation in order to do alternative dumping of instructions, instead of using MI->dump(), which can get a bit messy. Is there any way to access this object or the assembler strings? It seems that even these strings / methods are not available through any static methods. Does it exist during the whole compilation or is it

Hi, I have a question regarding this method, as i have discovered a case where it seems very far from 'strict'. I had two MI's, A and B, where A is !isSafeToMove(): A B TwoAddress pass changes the order to B A , as it reschedules the LastKill MI (B). Is this a bug in TwoAdress, or is it the case that isSafeToMove() is weaker than isSchedulingBoundary() so that these indirect violations are expected and accepted in TwoAddress and elsewhere? Thanks, Jonas

Thank you Chris. I will try to implement the TwoAddress pass to run on machine code. Why it has not been originally implemented to run on machine code? Is there anything that makes it troublesome after RA has been performed? Could you tell me if the transformations below are correct? 1) a := b op c --> a := b --> a := b...

On Tue, Mar 22, 2016 at 5:13 PM Eric Christopher wrote: > I think we can probably go ahead and throw this up on Phabricator for > review. I'd probably bring in Matthias for review as well. > > Thanks! > > -eric > (Follow up on the discuss in IRC) I tried to bridge PPC backend and commuteInstruction, not sure if correctly, but here I got some non-optimal results: in 12

> > Thank you Chris. I will try to implement the TwoAddress pass to run on > > machine code. Why it has not been originally implemented to run on > > machine code? > > I'm not sure what you mean. It definitely does run on machine code. I was thinking that it only transformed instructions with virtual registers because of this code in...

On Mon, 26 Jun 2006, Fernando Magno Quintao Pereira wrote: > Thank you Chris. I will try to implement the TwoAddress pass to run on > machine code. Why it has not been originally implemented to run on > machine code? I'm not sure what you mean. It definitely does run on machine code. > Is there anything that makes it troublesome after RA > has been performed? Do you specifically mean removing...

...m-dev at lists.llvm.org> wrote: >> >> Hi, >> >> I have cases of instruction pairs, where one is cheaper 2-address, and the other 3-address. I would like to select the 2-addr instruction during isel, but use the 3-addr instruction to avoid a copy if possible. I find that TwoAddressInstructionPass::isProfitableToConv3Addr() is only checking >> for the case of a physreg copy, and so leaves the majority of cases as they are (2-address). >> >> I would like to say "If 3-addr version would avoid a copy, use it!". Does anyone else have a similar situatio...

On Mon, 26 Jun 2006, Fernando Magno Quintao Pereira wrote: >>> Thank you Chris. I will try to implement the TwoAddress pass to run on >>> machine code. Why it has not been originally implemented to run on >>> machine code? >> >> I'm not sure what you mean. It definitely does run on machine code. > > I was thinking that it only transformed instructions with virtual > regis...

On Mon, 26 Jun 2006, Fernando Magno Quintao Pereira wrote: > The problem is that, after the TwoAddressInstructionPass is used, the > code is no longer in SSA form, and my register allocator rely on > some SSA properties. I am using the Spiller in VirtRegMap.* to generate > the code, but the incorrect mapping still happens when I invoke the > setReg() method directly on machine operands....

So what is the status about LiveVariables. Is there a plan to remove it? After searching in old lvm-dev-mails it is mentioned that LiveVariable still exists due to one pass needing it. And a comment in TargetPassConfig.cpp indicates that the pass in question is TwoAddressInstruction: // FIXME: Once TwoAddressInstruction pass no longer uses kill flags, // LiveVariables can be removed completely, and LiveIntervals can be directly // computed. (We still either need to regenerate kill flags after regalloc, or // preferably fix the scavenger to not depend on the...

Chris Lattner wrote: > On Thu, 2 Dec 2004, Brent Monroe wrote: > >>I'm trying to add the xadd instruction to the X86 back end. >>xadd r/m32, r32 >>exchanges r/m32 and r32, and loads the sum into r/m32. I'm >>interested in the case where the destination operand is a >>memory location. >> >>I've added the following entry to

...movsbl (%eax), %ecx movsbl 1(%eax), %eax addl %ecx, %ecx imull %ecx, %eax movl %eax, 4(%esp) movl $.str_1, (%esp) call printf #IMPLICIT_DEF %eax addl $12, %esp ret .size main, .-main On the other hand, if I use the TwoAddressInstructionPass, then llvm produces this code here: FNSTCW16m := MOV8mi := FLDCW16m := MOV32rm EAX := MOV32rm EAX := EAX MOVSX32rm8 ECX := EAX MOVSX32rm8 EAX := EAX ADJCALLSTACKDOWN := ADD32rr...

> > PHIElim and TwoAddress passes leave SSA form. > May be a missed something in your code but %vreg48 seems to be there > after PHI elimination. PHIElim tags those kind of registers as being > PHIJoin regs, updating LiveVariables pass, so the regcoalescer is aware > of them (some SSA info is still alive but t...

... : Ivan Llopard <ivanllopard at gmail.com> > Cc : "llvmdev at cs.uiuc.edu" <llvmdev at cs.uiuc.edu> > Envoyé le : Jeudi 25 octobre 2012 17h54 > Objet : Re: [LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG. > > > >> >> PHIElim and TwoAddress passes leave SSA form. >> May be a missed something in your code but %vreg48 seems to be there >> after PHI elimination. PHIElim tags those kind of registers as being >> PHIJoin regs, updating LiveVariables pass, so the regcoalescer is aware >> of them (some SSA info...

...body block that can modify vreg48 value, and thus vreg6 value. > I don't know if I should manually tell the pass that it's not in SSA mode (I assume that previous pass like 2 address simplification pass does it), if I miss something in my LLVM IR, > or if it's a bug. PHIElim and TwoAddress passes leave SSA form. May be a missed something in your code but %vreg48 seems to be there after PHI elimination. PHIElim tags those kind of registers as being PHIJoin regs, updating LiveVariables pass, so the regcoalescer is aware of them (some SSA info is still alive but the reg coalescer wil...

Hi, I don't know if my llvm ir code is faulty, or if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below. The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is : // BEFORE LOOP ... Some COPYs.... 400B%vreg47<def> = COPY %vreg2<kill>; R600_Reg32:%vreg47,%vreg2