search for: twoaddr

...hat they can be rerun as needed? Is all but LiveIntervals > ok with this as of now? So the good news is that we are slowly moving towards a similar design. The bad news is that we are *slowly* moving... Currently, the register allocator super-pass contains these passes: - LiveVars - PhiElim - TwoAddr - LiveIntervals - Coalescing - RegAlloc Currently, LiveVars requires SSA form, and LiveIntervals only works with simple multi-defs as produced by PhiElim and TwoAddr. That means the pass order is fixed. The plan is to teach PhiELim and TwoAddr how to update LiveIntervals so it can run earlier: -...

Hi (Jakob), in reference to the prior message below, I have the following follow-up questions, as I also need a scheduling pass prior to regalloc. I need to do this in order to set VLIW-flags, so that the RA is aware of several MI's per cycle with a redefined LiveRange::overlap-function. On a multiple-issue cycle, a register that gets killed can be reused by another MI - these live ranges do

Hi, thank you for your explanations. In order to get a pre-RA scheduling, I would need something like: - LiveVars - PhiElim - TwoAddr - LiveIntervals - Coalescing - Scheduler (new) - SlotIndexing - LiveIntervals2 (new) - RegAllocMy qeustion then is, is it really so difficult to create the live intervals information, with modifications to the original algorithm, or even from scratch? Normally, it should not have to be diffi...

Hi, I have cases of instruction pairs, where one is cheaper 2-address, and the other 3-address. I would like to select the 2-addr instruction during isel, but use the 3-addr instruction to avoid a copy if possible. I find that TwoAddressInstructionPass::isProfitableToConv3Addr() is only checking for the case of a physreg copy, and so leaves the majority of cases as they are (2-address). I would like to say "If 3-addr version would avoid a copy, use it!". Does anyone else have a similar situation? To do this, one w...

On Apr 8, 2011, at 9:56 AM, NAKAMURA Takumi wrote: >>> 8B C3 mov eax, ebx >>> 03 C1 add eax, ecx >>> becomes >>> 8B C3 03 C1 add eax, ebx, ecx > > In my understanding, twoaddr pass tends to emit such a sequence. Yes, it always does, and the coalescer tries very hard to eliminate the copy. > Though I don't have sandybridge, I have not measured. > Prior processors(intel and amd) might spend 1 ALU to execute "mov", > then mov - add must have depende...

>>                 8B C3 mov eax, ebx >>                 03 C1 add eax, ecx >> becomes >>                 8B C3 03 C1 add eax, ebx, ecx In my understanding, twoaddr pass tends to emit such a sequence. Though I don't have sandybridge, I have not measured. Prior processors(intel and amd) might spend 1 ALU to execute "mov", then mov - add must have dependency. In contrast, the sequence below might be executed in parallel; mov %ebx, %eax add %ecx,...

On Apr 8, 2011, at 3:29 AM, Nicolas Capens wrote: > x86 processors use macro-op fusion to merge together two instructions and execute them as one. So it's beneficial for the compiler to emit them as a pair. > > Currently only compare and jump instructions get fused though. And I was wondering whether it also makes sense to fuse move and arithmetic instructions together, to form

...m-dev at lists.llvm.org> wrote: >> >> Hi, >> >> I have cases of instruction pairs, where one is cheaper 2-address, and the other 3-address. I would like to select the 2-addr instruction during isel, but use the 3-addr instruction to avoid a copy if possible. I find that TwoAddressInstructionPass::isProfitableToConv3Addr() is only checking >> for the case of a physreg copy, and so leaves the majority of cases as they are (2-address). >> >> I would like to say "If 3-addr version would avoid a copy, use it!". Does anyone else have a similar situa...

...; > On Apr 8, 2011, at 9:56 AM, NAKAMURA Takumi wrote: > > >>> 8B C3 mov eax, ebx > >>> 03 C1 add eax, ecx > >>> becomes > >>> 8B C3 03 C1 add eax, ebx, ecx > > > > In my understanding, twoaddr pass tends to emit such a sequence. > > Yes, it always does, and the coalescer tries very hard to eliminate the > copy. > > > Though I don't have sandybridge, I have not measured. > > Prior processors(intel and amd) might spend 1 ALU to execute "mov", > >...

On Thu, May 26, 2011 at 15:07:24 +0200, Jonas Paulsson wrote: > In order to get a pre-RA scheduling, I would need something like: > - LiveVars > - PhiElim > - TwoAddr > - LiveIntervals > - Coalescing > - Scheduler (new) > - SlotIndexing > - LiveIntervals2 (new) > - RegAlloc > My qeustion then is, is it really so difficult to create the live intervals information, with modifications to the original algorithm, or even from scratch? I...