Displaying 3 results from an estimated 3 matches for "tuples2dspc".
2012 Jul 17
0
[LLVMdev] Switching between sibling/cousin registers via API calls
Hi Micah,
This sounds somewhat similar to what ARM uses for the stride-by-two vector load instructions. For example, Tuples2DSpc. While not exactly what you're looking for, perhaps something along those lines would work?
-Jim
On Jul 17, 2012, at 3:24 PM, "Villmow, Micah" <Micah.Villmow at amd.com> wrote:
> I have a register hierarchy that looks like a binary tree.
> v4 -> {v2, v2} -> {s, s}...
2012 Jul 17
2
[LLVMdev] Switching between sibling/cousin registers via API calls
I have a register hierarchy that looks like a binary tree.
v4 -> {v2, v2} -> {s, s}{s, s}(or, {x, y}, {z, w})
I have an instruction that can access the 2nd and/or 4th scalar and an
instruction that can access the 1st and/or 3rd scalar. What I need to do
is that given the first scalar, I need to be able to select the 2nd scalar,
or/and given the 3rd, select the 4th. I define a sibling
2017 Sep 10
2
Question about quad-register
Hi All,
If the target supports quad-register R0:R1:R2:R3 (Rn is 32-bit
register), is it possible mapping quad-register
to v4i32 so that the following example work?
typedef int v4si __attribute__ ((vector_size (16)));
void foo(v4si i) {
v4si j = i;
}
I don't know how to write CallingConv.td to represent the concept of
occupying quad-register R0:R1:R2:R3
once seeing