search for: ttm_pl_tt

On Wed, Sep 04, 2013 at 08:59:13AM +0200, Maarten Lankhorst wrote: > > When looking into this bug I noticed that nouveau_bo_vma_add needs to have a check for nvbo->page_shift == vma->vm->vmm->spg_shift, > and only if the check is true it should map the page in TTM_PL_TT. Patch below. > Should probably also be cc'd to stable. > How about this patch? Is it ready to go in? Thanks, -- Pasi > ~Maarten > > diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c > index 89b992e..355a1b7 100644 > --- a/driv...

...uveau_bo.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c @@ -471,15 +471,9 @@ static inline uint32_t nouveau_bo_mem_ctxdma(struct nouveau_bo *nvbo, struct nouveau_channel *chan, struct ttm_mem_reg *mem) { - if (chan == nouveau_bdev(nvbo->bo.bdev)->channel) { - if (mem->mem_type == TTM_PL_TT) - return NvDmaGART; - return NvDmaVRAM; - } - if (mem->mem_type == TTM_PL_TT) - return chan->gart_handle; - return chan->vram_handle; + return NvDmaGART; + return NvDmaVRAM; } static int @@ -495,22 +489,11 @@ nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool in...

...= TTM_PL_FLAG_UNCACHED | + TTM_PL_FLAG_WC; + man->default_caching = TTM_PL_FLAG_WC; + + man->io_addr = NULL; + man->io_offset = drm_get_resource_start(dev, 1); + man->io_size = drm_get_resource_len(dev, 1); + man->gpu_offset = dev_priv->vm_vram_base; + break; + } case TTM_PL_TT: switch (dev_priv->gart_info.type) { case NOUVEAU_GART_AGP: @@ -564,6 +582,7 @@ nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp) static uint32_t nouveau_mem_prios[] = { TTM_PL_PRIV0, + TTM_PL_PRIV1, TTM_PL_VRAM, TTM_PL_TT, TTM_PL_SYSTEM @@ -571,6 +590,7...

Commit a55409066 ("drm/nv50-: map TTM_PL_SYSTEM through a BAR for CPU access") made it possible to work with tiled memory. However mem->mm_node is not a nouveau_mem for AGP-using pre-NV50 cards, but a drm_mm_node, as created by the ttm_bo_manager_func. As such, extend the untiled check to explicitly include all pre-nv50 cards. Reported-by: Ronald <ronald645 at gmail.com>

On Thu, Aug 22, 2013 at 5:12 PM, Maarten Lankhorst <maarten.lankhorst at canonical.com> wrote: > Op 22-08-13 02:10, Ilia Mirkin schreef: >> The code expects non-VRAM mem nodes to have a pages list. If that's not >> set, it will do a null deref down the line. Warn on that condition and >> return an error. >> >> See

...; + } + return; + } + list_for_each_entry(vma, &nvbo->vma_list, head) { - if (new_mem && new_mem->mem_type == TTM_PL_VRAM) { + if (new_mem->mem_type == TTM_PL_VRAM) { nouveau_vm_map(vma, new_mem->mm_node); - } else - if (new_mem && new_mem->mem_type == TTM_PL_TT && - nvbo->page_shift == vma->vm->vmm->spg_shift) { + } else if (new_mem->mem_type == TTM_PL_TT && + nvbo->page_shift == vma->vm->vmm->spg_shift) { if (((struct nouveau_mem *)new_mem->mm_node)->sg) nouveau_vm_map_sg_table(v...

...it for now and only enable it if > there is a good reason to do so. > > Signed-off-by: Christian K?nig <christian.koenig at amd.com> So a lot more work, and more risk (but hey it's agp, how busted can it get) could be to demidlayer this. I.e. a small set of helpers to create a TTM_PL_TT manager, backed by agp. With zero agp code remaining in ttm itself, and all the ttm agp code moved out to a ttm-agp-helper.ko module that drivers would call. But again a lot of work, so really only an option if we can't sunset agp directly. -Daniel > --- > drivers/gpu/drm/Kconfig...

...find any other places that attempt to move buffers to VRAM though, so it's probably harmless. When looking into this bug I noticed that nouveau_bo_vma_add needs to have a check for nvbo->page_shift == vma->vm->vmm->spg_shift, and only if the check is true it should map the page in TTM_PL_TT. Patch below. Should probably also be cc'd to stable. ~Maarten diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c index 89b992e..355a1b7 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c @@ -1560,7 +1560,8 @@ nou...

On 04/17/2015 02:25 PM, Alexandre Courbot wrote: > On Thu, Apr 16, 2015 at 8:06 PM, Vince Hsu <vinceh at nvidia.com> wrote: >> Hi, >> >> Generally the the imported buffers which has memory type TTM_PL_TT are >> mapped as small pages probably due to lack of big page allocation. But the >> platform device which also use memory type TTM_PL_TT, like GK20A, can > Nit: GK20A can *only* allocate GPU memory from TTM_PL_TT. Trying to > allocate from VRAM will result in an error. Yep. >...

...ouveau_drm *drm, struct ttm_mem_reg *reg) > +{ > + struct nouveau_mem *mem = nouveau_mem(reg); > + > + if (!reg->bus.base) > + return; /* already freed */ > + > + if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) { > + switch (reg->mem_type) { > + case TTM_PL_TT: > + if (mem->kind) > + nvif_object_unmap_handle(&mem->mem.object); > + break; > + case TTM_PL_VRAM: > + nvif_object_unmap_handle(&mem->mem.object); > + break; > + default: > + break; > + } > + } > + reg->bus.base = 0; > +} &gt...

...struct nouveau_mem *mem = nouveau_mem(reg); > + > + if (!reg->bus.base) > + return; /* already freed */ > + > + if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) { > + switch (reg->mem_type) { > + case TTM_PL_TT: > + if (mem->kind) > + nvif_object_unmap_handle(&mem->mem.object); > + break; > + case TTM_PL_VRAM: > + nvif_object_unmap_handle(&mem->mem.object); > +...

...buffers. > Using the write-combining buffer doesn't need any additional > synchronization as it will get flushed on pushbuf kickoff anyways. I tried to go that way, and something interesting happened. What I did: remove this patch and instead set the following caching parameters for the TTM_PL_TT case in nouveau_bo_init_mem_type(): man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC; man->default_caching = TTM_PL_FLAG_WC; What happened: no runtime errors as what happened when caching is enabled. However, many of the vertex and texture buffers seem to be partially...

...s/gpu/drm/nouveau/nouveau_bo.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c @@ -1551,7 +1579,8 @@ nouveau_bo_vma_add(struct nouveau_bo *nvbo, struct nouveau_vm *vm, if (nvbo->bo.mem.mem_type == TTM_PL_VRAM) nouveau_vm_map(vma, nvbo->bo.mem.mm_node); - else if (nvbo->bo.mem.mem_type == TTM_PL_TT) { + else if (nvbo->bo.mem.mem_type == TTM_PL_TT && + nvbo->page_shift == vma->vm->vmm->spg_shift) { if (node->sg) nouveau_vm_map_sg_table(vma, 0, size, node); else

...s/gpu/drm/nouveau/nouveau_bo.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c @@ -1549,7 +1549,8 @@ nouveau_bo_vma_add(struct nouveau_bo *nvbo, struct nouveau_vm *vm, if (nvbo->bo.mem.mem_type == TTM_PL_VRAM) nouveau_vm_map(vma, nvbo->bo.mem.mm_node); - else if (nvbo->bo.mem.mem_type == TTM_PL_TT) { + else if (nvbo->bo.mem.mem_type == TTM_PL_TT && + nvbo->page_shift == vma->vm->vmm->spg_shift) { if (node->sg) nouveau_vm_map_sg_table(vma, 0, size, node); else -- 1.8.4

...+ /* Supported placements are %TTM_PL_VRAM and %TTM_PL_SYSTEM */ > >> + struct ttm_placement placement; > >> + struct ttm_place placements[3]; > > > > placements[2] should be enough I guess? > > TTM_PL_VRAM has index 2 and TTM_PL_SYSTEM has index 0. There's TTM_PL_TT > at index 1. We don't use all three array entries here, but I'm not sure > if something in TTM does. I took the line from the drivers and didn't > change it for that reason. TTM_PL_* isn't an index into that array. See drm_gem_vram_placement() which fills that array. It...

Hi guys, I've already send this out in September last year, but only got a response from Daniel. Could you guys please test this and tell me what you think about it? Basically I'm trying to remove all driver specific features from TTM which don't need to be inside the framework. Thanks, Christian.

...void +nouveau_ttm_io_mem_free_locked(struct nouveau_drm *drm, struct ttm_mem_reg *reg) +{ + struct nouveau_mem *mem = nouveau_mem(reg); + + if (!reg->bus.base) + return; /* already freed */ + + if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) { + switch (reg->mem_type) { + case TTM_PL_TT: + if (mem->kind) + nvif_object_unmap_handle(&mem->mem.object); + break; + case TTM_PL_VRAM: + nvif_object_unmap_handle(&mem->mem.object); + break; + default: + break; + } + } + reg->bus.base = 0; +} + static int nouveau_ttm_io_mem_reserve(struct ttm_bo_device...

...nouveau_drm *drm, + struct ttm_resource *reg) +{ + struct nouveau_mem *mem = nouveau_mem(reg); + + if (!reg->bus.base && !reg->bus.offset) + return; /* already freed */ + + if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) { + switch (reg->mem_type) { + case TTM_PL_TT: + if (mem->kind) + nvif_object_unmap_handle(&mem->mem.object); + break; + case TTM_PL_VRAM: + nvif_object_unmap_handle(&mem->mem.object); + break; + default: + break; + } + } + reg->bus.base = 0; + reg->bus.offset = 0; +} + static int nouveau_ttm_io_mem_res...

...dn't create... */ if (bo->destroy != nouveau_bo_del_ttm) return; list_for_each_entry(vma, &nvbo->vma_list, head) { - if (new_mem && new_mem->mem_type == TTM_PL_VRAM) { + if (!new_mem || + old_mem->mem_type == TTM_PL_VRAM || + (old_mem->mem_type == TTM_PL_TT && + nvbo->page_shift == vma->vm->vmm->spg_shift)) + nouveau_vm_unmap(vma); + + if (!new_mem) + continue; + + if (new_mem->mem_type == TTM_PL_VRAM) { nouveau_vm_map(vma, new_mem->mm_node); } else if (new_mem && new_mem->mem_type == TTM_P...

...ouveau_drm *drm, struct ttm_mem_reg *reg) > +{ > + struct nouveau_mem *mem = nouveau_mem(reg); > + > + if (!reg->bus.base) > + return; /* already freed */ > + > + if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) { > + switch (reg->mem_type) { > + case TTM_PL_TT: > + if (mem->kind) > + nvif_object_unmap_handle(&mem->mem.object); > + break; > + case TTM_PL_VRAM: > + nvif_object_unmap_handle(&mem->mem.object); > + break; > + default: > + break; > + } > + } > + reg->bus.base = 0; > +} &gt...