search for: tt_cached

...100644 > --- a/drivers/gpu/drm/nouveau/nouveau_bo.c > +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c > @@ -411,6 +411,10 @@ nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible, > { > int ret; > > + if (nvbo->bo.ttm && nvbo->bo.ttm->caching_state == tt_cached) You don't want to do it also for tt_wc ? > + ttm_dma_tt_cache_sync_for_device((struct ttm_dma_tt *)nvbo->bo.ttm, > + &nouveau_bdev(nvbo->bo.ttm->bdev)->dev->pdev->dev); > + > ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement, >...

...> +nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo) > +{ > + struct nouveau_device *device; > + struct ttm_tt *ttm = nvbo->bo.ttm; > + > + device = nouveau_dev(nouveau_bdev(ttm->bdev)->dev); > + > + if (nvbo->bo.ttm && nvbo->bo.ttm->caching_state == tt_cached) > + ttm_dma_tt_cache_sync_for_cpu((struct ttm_dma_tt *)nvbo->bo.ttm, > + nv_device_base(device)); Can we be certain at this point that the struct ttm_tt is in fact a struct ttm_dma_tt? > diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.h b/drivers/gpu/drm/nouveau/nouveau_bo...

...drm/nouveau/nouveau_bo.c > > +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c > > @@ -411,6 +411,10 @@ nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible, > > { > > int ret; > > > > + if (nvbo->bo.ttm && nvbo->bo.ttm->caching_state == tt_cached) > > You don't want to do it also for tt_wc ? > No the point of using writecombined memory for BOs is to explicitly avoid the need for this cache sync. An uncached MMIO read from the device should already flush out all writecombining buffers and this read is always happening when sub...

...ouveau_bo.c index af20fba..f4a2eb9 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c @@ -411,6 +411,10 @@ nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible, { int ret; + if (nvbo->bo.ttm && nvbo->bo.ttm->caching_state == tt_cached) + ttm_dma_tt_cache_sync_for_device((struct ttm_dma_tt *)nvbo->bo.ttm, + &nouveau_bdev(nvbo->bo.ttm->bdev)->dev->pdev->dev); + ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement, interruptible, no_wait_gpu); if (ret) diff --git a/drivers/gpu/drm/n...

...+#ifdef NOUVEAU_NEED_CACHE_SYNC +void +nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo) +{ + struct nouveau_device *device; + struct ttm_tt *ttm = nvbo->bo.ttm; + + device = nouveau_dev(nouveau_bdev(ttm->bdev)->dev); + + if (nvbo->bo.ttm && nvbo->bo.ttm->caching_state == tt_cached) + ttm_dma_tt_cache_sync_for_cpu((struct ttm_dma_tt *)nvbo->bo.ttm, + nv_device_base(device)); +} + +void +nouveau_bo_sync_for_device(struct nouveau_bo *nvbo) +{ + struct ttm_tt *ttm = nvbo->bo.ttm; + + if (ttm && ttm->caching_state == tt_cached) { + struct nouveau_devi...

...> @@ -258,12 +274,7 @@ int ttm_dma_tt_init(struct ttm_dma_tt *ttm_dma, struct ttm_bo_device *bdev, > { > struct ttm_tt *ttm = &ttm_dma->ttm; > > - ttm->bdev = bdev; > - ttm->num_pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT; > - ttm->caching_state = tt_cached; > - ttm->page_flags = page_flags; > - ttm->state = tt_unpopulated; > - ttm->swap_storage = NULL; > + ttm_tt_init_fields(ttm, bdev, size, page_flags); > > INIT_LIST_HEAD(&ttm_dma->pages_list); > if (ttm_dma_tt_alloc_page_directory(ttm_dma)) { > @@ -2...

This is the first set of patches to make Nouveau work on Tegra. Those are only the obvious correctness fixes, a lot of optimization work remains to be done, but at least it's enough to get accel working and let the machine survive a piglit run. A new BO flag is introduced to allow userspace to hint the kernel about possible optimizations. Lucas Stach (6): drm/ttm: recognize ARM arch in

This small series introduces TTM helper functions as well as Nouveau hooks that are needed to ensure buffer coherency on ARM. Most of this series is a forward-port of some patches Lucas Stach sent last year and that are also needed for Nouveau GK20A support: http://lists.freedesktop.org/archives/nouveau/2013-August/014026.html Another patch takes care of flushing the CPU write-buffer when

For this v2 I have fixed the patches that are non-controversial (all Lucas' :)) and am resubmitting them in the hope that they will get merged. This will just leave the issue of Nouveau system-memory buffers mapping to be solved. This issue is quite complex, so let me summarize the situation and the data I have at hand. ARM caching is like a quantum world where Murphy's law constantly

...a_tt_init(struct ttm_dma_tt *ttm_dma, >> struct ttm_bo_device *bdev, >>   { >>       struct ttm_tt *ttm = &ttm_dma->ttm; >>   -    ttm->bdev = bdev; >> -    ttm->num_pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT; >> -    ttm->caching_state = tt_cached; >> -    ttm->page_flags = page_flags; >> -    ttm->state = tt_unpopulated; >> -    ttm->swap_storage = NULL; >> +    ttm_tt_init_fields(ttm, bdev, size, page_flags); >>         INIT_LIST_HEAD(&ttm_dma->pages_list); >>       if (ttm_dma_tt_alloc_p...

On Mon, Jan 11, 2010 at 10:13 AM, Xavier <shiningxc at gmail.com> wrote: > [ ?268.666662] reserve_ram_pages_type failed 0x9cba000-0x9cbb000, > track 0x8, req 0x10 > [ ?269.001031] reserve_ram_pages_type failed 0x6ff0000-0x6ff1000, > track 0x8, req 0x10 > [ ?269.474134] reserve_ram_pages_type failed 0x68f2000-0x68f3000, > track 0x8, req 0x10 > [ ?269.767270]