search for: tsx

fSeries Technical Analysis rsiTA problem Hello, I?m trying to use the rsiTA() function but keep getting this error: >rsiTA(tsx,14) Error in "[.timeSeries"(close, 1:(length(close) - 1)) : only 0's may be mixed with negative subscripts Here?s is the first three lines of my data: >tsx[1:3,] close 2004-04-18 20:00:00 8702.82 2004-04-19 20:00:00 8602.98 2004-04-20 20:0...

...everyone I've got a problem regarding the arima() and the ar() function for autoregressive series. I would simply like to combine them. To better understand my question, I first show you how I'm using these two functions individually (see file in the attachement). 1) apply(TSX,2, function(x) ar(na.omit(x),method="mle")$order # this function finds the optimal (autoregressive) order for each series (briefly speaking: for each series I get a specific number) 2) apply(TSX,2,function(x)arima(x,order=c(1,0,0))$residuals # this function puts an autoregressive mo...

Hi I wonder, if live migration (back and forth) is possible on mixed Haswell (Xeon V3) and Broadwell (Xeon V4) installations. The only notable difference between the two is apparently a working TSX implementation on V4, which got disabled on V3 due to bugs. The rest (VMCS-shadowing, posted interrupts) should not apply to our environment, as we do not run nested-vmx nor device-passthrough on our Xen servers. Now, I found no sane way to disable TSX on a given system but I cannot rule out,...

...99ccf6 in handle_incoming_sdp (session=0x7fba3c031200, sdp=0x7fba3c0adfb8) at res_pjsip_session.c:243 #3 0x00007fba0499e650 in session_inv_on_rx_offer (inv=0x7fba3c0504e8, offer=0x7fba3c0adfb8) at res_pjsip_session.c:3009 #4 0x00007fba44b1b501 in inv_check_sdp_in_incoming_msg (inv=0x7fba3c0504e8, tsx=0x7fba08006878, rdata=0x7fba3c0b00a8) at ../src/pjsip-ua/sip_inv.c:2110 #5 0x00007fba44b20026 in inv_on_state_confirmed (inv=0x7fba3c0504e8, e=0x7fb9f5901880) at ../src/pjsip-ua/sip_inv.c:4869 #6 0x00007fba44b18869 in mod_inv_on_tsx_state (tsx=0x7fba08006878, e=0x7fb9f5901880) at ../src/pjsip-ua/...

Here is the patch 0004-Enable-HLE-code-generation.patch Yours - Michael On Tue, 2013-02-19 at 14:07 -0800, Michael Liao wrote: > Hi All, > > I'd like to add HLE support in LLVM/clang consistent to GCC's style [1]. > HLE from Intel TSX [2] is legacy compatible instruction set extension to > specify transactional region by adding XACQUIRE and XRELEASE prefixes. > To support that, GCC chooses the approach by extending the memory order > flag in __atomic_* builtins with target-specific memory model in high > bits (bit 31...

Here is the patch 0002-Add-HLE-target-feature.patch Yours - Michael On Tue, 2013-02-19 at 14:07 -0800, Michael Liao wrote: > Hi All, > > I'd like to add HLE support in LLVM/clang consistent to GCC's style [1]. > HLE from Intel TSX [2] is legacy compatible instruction set extension to > specify transactional region by adding XACQUIRE and XRELEASE prefixes. > To support that, GCC chooses the approach by extending the memory order > flag in __atomic_* builtins with target-specific memory model in high > bits (bit 31...

Here is the patch 0003-Add-XACQ-XREL-prefix-and-encoding-asm-printer-suppor.patch Yours - Michael On Tue, 2013-02-19 at 14:07 -0800, Michael Liao wrote: > Hi All, > > I'd like to add HLE support in LLVM/clang consistent to GCC's style [1]. > HLE from Intel TSX [2] is legacy compatible instruction set extension to > specify transactional region by adding XACQUIRE and XRELEASE prefixes. > To support that, GCC chooses the approach by extending the memory order > flag in __atomic_* builtins with target-specific memory model in high > bits (bit 31...

...on for including it in LLVM. > > Thanks, > Nadav > > > On Feb 19, 2013, at 11:52 AM, Michael Liao <michael.liao at intel.com> wrote: > >> Hi All, >> >> I'd like to add HLE support in LLVM/clang consistent to GCC's style [1]. HLE from Intel TSX [2] is legacy compatible instruction set extension to >> specify transactional region by adding XACQUIRE and XRELEASE prefixes. To support that, GCC chooses the approach by extending the memory order >> flag in __atomic_* builtins with target-specific memory model in high bits (bit 31-1...

...nd I am not sure that I understand the motivation for including it in LLVM. Thanks, Nadav On Feb 19, 2013, at 11:52 AM, Michael Liao <michael.liao at intel.com> wrote: > Hi All, > > I'd like to add HLE support in LLVM/clang consistent to GCC's style [1]. HLE from Intel TSX [2] is legacy compatible instruction set extension to > specify transactional region by adding XACQUIRE and XRELEASE prefixes. To support that, GCC chooses the approach by extending the memory order > flag in __atomic_* builtins with target-specific memory model in high bits (bit 31-16 for ta...

Hi All, I'd like to add HLE support in LLVM/clang consistent to GCC's style [1]. HLE from Intel TSX [2] is legacy compatible instruction set extension to specify transactional region by adding XACQUIRE and XRELEASE prefixes. To support that, GCC chooses the approach by extending the memory order flag in __atomic_* builtins with target-specific memory model in high bits (bit 31-16 for target-speci...

Hi All, I'd like to add HLE support in LLVM/clang consistent to GCC's style [1]. HLE from Intel TSX [2] is legacy compatible instruction set extension to specify transactional region by adding XACQUIRE and XRELEASE prefixes. To support that, GCC chooses the approach by extending the memory order flag in __atomic_* builtins with target-specific memory model in high bits (bit 31-16 for target-speci...

On Fri, Sep 19, 2014 at 03:06:55PM -0700, Andy Lutomirski wrote: > On Fri, Sep 19, 2014 at 3:05 PM, Theodore Ts'o <tytso at mit.edu> wrote: > > On Fri, Sep 19, 2014 at 09:40:42AM -0700, H. Peter Anvin wrote: > >> > >> There is a huge disadvantage to the fact that CPUID is a user space > >> instruction, though. > > > > But if the goal is to

On Fri, Sep 19, 2014 at 03:06:55PM -0700, Andy Lutomirski wrote: > On Fri, Sep 19, 2014 at 3:05 PM, Theodore Ts'o <tytso at mit.edu> wrote: > > On Fri, Sep 19, 2014 at 09:40:42AM -0700, H. Peter Anvin wrote: > >> > >> There is a huge disadvantage to the fact that CPUID is a user space > >> instruction, though. > > > > But if the goal is to

...quot;,0093d5ac,0093d5a4,a2000000) ret=6833676d 0021:Ret shlwapi.UrlCanonicalizeA() retval=00000000 ret=6833676d 0021:Ret wininet.InternetCanonicalizeUrlA() retval=00000001 ret=0051cc6d 0021:Call wininet.InternetCanonicalizeUrlA(005dfac0 "http://www.trading-tools.com/mld/symbol lists71/Canada/TSX.txt",0093d5ac,0093d5a4,02000000) ret=0051cc6d 0021:Call shlwapi.UrlCanonicalizeA(005dfac0 "http://www.trading-tools.com/mld/symbol lists71/Canada/TSX.txt",0093d5ac,0093d5a4,a2000000) ret=6833676d 0021:Ret shlwapi.UrlCanonicalizeA() retval=00000000 ret=6833676d 0021:Ret wininet.Inte...

...hat package contains the algorithm to do probit model. Lawrence N.M Kazembe Mathematical Sciences Department Chancellor College University of Malawi P.O. Box 280 Zomba Malawi Tel: (265) 524 222 ext 284 Fax: (265) 524 046 e-mail: lkazembe at chirunga.sdnp.org.mw url: kazembe.cjb.net kazembe.tsx.org -.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.- r-help mailing list -- Read http://www.ci.tuwien.ac.at/~hornik/R/R-FAQ.html Send "info", "help", or "[un]subscribe" (in the "body", not the subject !) To: r-help-request at...

Hi all, I got a new laptop recently and what worked before no longer works (Fedora 23 on the laptops in both cases)... I'm trying to get nested virtualization to work because I use the VMs on the laptop to simulate an HA cluster that itself hosts VMs. I don't care much at all about the performance of the nested VM, it's just there so that I can work on the cluster's code.

...ed while handling ANSWER and before generating the 200OK response. Looking at the core file we see that the problem is in - pjsip/src/pjsip/sip_transaction.c line 3158 : PJ_ASSERT_RETURN(event->type == PJSIP_EVENT_TX_MSG && event->body.tx_msg.tdata == tsx->last_tx, PJ_EINVALIDOP); After investigating further I came to a conclusion that the second expression fails (marked with yellow), and that causes the Asterisk to crash. I have already removed the expression and logged whenever this expression fails. It seems to work...

...ce the CPU load. > > The main difference between the setups is that the older laptop had a > Sandy bridge(? Thinkpad W530) and the new laptop is a Broadwell > (Thinkpad P70). [A side note on Broadwell CPUs, you might've noticed by now: Intel released a microcode update to remove TSX; if you're using the model without the TSX, your guest hypervisor (L1) should be using the CPU model Haswell-noTSX.] > I've tried to loading vhost_net without much luck. What is preventing you from loading `vhost_net`? Assuming VHOST_NET is compiled in your Kernel, `sudo modprobe v...

...temd start script we are using chan_pjsip only for webrtc endpoints . switched from sipml5 to jssip with upgrade to 13.15.0(from 13.9.0) few days ago today i have problems with stopping/crashing asterisk /var/log/asterisk/messages dont show any clues [May 9 12:10:52] WARNING[25762] pjproject: tsx0x7fbb28024088 ..Error sending Response msg 200/REGISTER/cseq=4 (tdta0x7fbb080d29e8): Unknown Error (PJ_EUNKNOWN) [May 9 12:10:54] WARNING[6458] pjproject: tsx0x7fbb28024088 ..Error sending Response msg 200/REGISTER/cseq=4 (tdta0x7fbb382be318): Unknown Error (PJ_EUNKNOWN) [May 9 12:10:54] WARN...

...ug 27 07:51:36] DEBUG[605] res_pjsip/pjsip_resolver.c: [0x7f75282fe7f8] Resolution completed - 0 viable targets [Aug 27 07:51:36] DEBUG[595] res_pjsip/pjsip_resolver.c: [0x7f75282fe7f8] Invoking user callback with '0' addresses [Aug 27 07:51:36] DEBUG[595] res_pjsip.c: 0x7f75282eb150: PJSIP tsx response received [Aug 27 07:51:36] DEBUG[595] res_pjsip.c: 0x7f75282eb150: Cancelling timer [Aug 27 07:51:36] DEBUG[595] res_pjsip.c: 0x7f75282eb150: Timer cancelled [Aug 27 07:51:36] DEBUG[595] res_pjsip.c: 0x7f75282eb150: Callbacks executed [Aug 27 07:51:36] DEBUG[595] res_pjsip.c: 0x7f75282eb15...