search for: tstellar

On Thu, Apr 17, 2014 at 09:57:32AM -0400, Tom Stellard wrote: > On Fri, Apr 11, 2014 at 03:02:21PM -0700, Tom Stellard wrote: > > Hi, > > > > I have just tagged the first release candidate for the > > 3.4.1 release, so testers may begin testing. Please refer to > > http://llvm.org/docs/ReleaseProcess.html for information on how to > > validate a release.

...nt from a hash manually, better to have it in the email in the first place. You can’t rely on order-of-email-delivery to reflect order-of-commit. --paulr From: llvm-dev <llvm-dev-bounces at lists.llvm.org> On Behalf Of Shoaib Meenai via llvm-dev Sent: Wednesday, October 16, 2019 1:42 AM To: tstellar at redhat.com; Mehdi AMINI <joker.eph at gmail.com> Cc: llvm-dev <llvm-dev at lists.llvm.org>; cfe-dev <cfe-dev at lists.llvm.org>; openmp-dev (openmp-dev at lists.llvm.org) <openmp-dev at lists.llvm.org>; LLDB Dev <lldb-dev at lists.llvm.org> Subject: Re: [llvm-dev] [...

...att > > From: llvm-dev <llvm-dev-bounces at lists.llvm.org> on behalf of llvm-dev <llvm-dev at lists.llvm.org> > Reply-To: Neil Ryan <neilryan at cs.washington.edu> > Date: Wednesday, April 17, 2019 at 9:28 PM > To: llvm-dev <llvm-dev at lists.llvm.org>, "tstellar at redhat.com" <tstellar at redhat.com> > Subject: Re: [llvm-dev] Disable combining of loads and stores in instcombine > > I’m writing a pass for some custom hardware — we’d like to split arrays across hardware elements; this doesn’t work if consecutive writes to characters get...

On 10/15/2019 09:44 PM, Mehdi AMINI wrote: > > > On Tue, Oct 15, 2019 at 9:33 PM Tom Stellard <tstellar at redhat.com <mailto:tstellar at redhat.com>> wrote: > > On 10/15/2019 09:24 PM, Mehdi AMINI wrote: > > Hi Tom. > > > > One issue with this is that we don't have a clear "ordering" from linear revision numbers from these emails. Have...

...Russ > > On Thu, 9 Jan 2020 at 20:05, Tom Stellard via cfe-dev <cfe-dev at lists.llvm.org <mailto:cfe-dev at lists.llvm.org>> wrote: > > On 01/09/2020 09:11 AM, Brian Cain wrote: > > > > > > On Thu, Jan 9, 2020 at 12:29 AM Tom Stellard <tstellar at redhat.com <mailto:tstellar at redhat.com> <mailto:tstellar at redhat.com <mailto:tstellar at redhat.com>>> wrote: > > > > On 01/08/2020 09:24 AM, Brian Cain wrote: > > > Tom, the 9.0.1 final binaries didn't (yet?) make it to the...

On 10/16/2019 12:02 PM, Roman Lebedev wrote: > On Wed, Oct 16, 2019 at 9:55 PM Tom Stellard <tstellar at redhat.com> wrote: >> >> On 10/16/2019 07:31 AM, Roman Lebedev wrote: >>> +1, please. >>> >>> Also, putting a tag on the *first* commit in the repo, >>> and doing `git describe --match FIRST_COMMIT_TAG` will be *great*! >>> >> &gt...

...on the master branch. Given that we are close to the end of the 9.0.1 cycle, unless there are any strong objections, I would like to get this enabled by Mon Nov 18, to maximize its usefulness. Let me know what you think. Thanks, Tom [1] https://github.com/features/actions [2] https://github.com/tstellar/llvm-project/commit/952d80e8509ecc95797b2ddbf1af40abad2dcf4e/checks?check_suite_id=305765621 [3] https://github.com/tstellar/llvm-project/commit/6d74f1b81632ef081dffa1e0c0434f47d4954423/checks?check_suite_id=303074176 [4] https://github.com/tstellar/actions

...ace. You can’t rely on order-of-email-delivery to reflect order-of-commit. >> >> --paulr >> >> >> >> From: llvm-dev <llvm-dev-bounces at lists.llvm.org> On Behalf Of Shoaib Meenai via llvm-dev >> Sent: Wednesday, October 16, 2019 1:42 AM >> To: tstellar at redhat.com; Mehdi AMINI <joker.eph at gmail.com> >> Cc: llvm-dev <llvm-dev at lists.llvm.org>; cfe-dev <cfe-dev at lists.llvm.org>; openmp-dev (openmp-dev at lists.llvm.org) <openmp-dev at lists.llvm.org>; LLDB Dev <lldb-dev at lists.llvm.org> >> Subject...

I’m writing a pass for some custom hardware — we’d like to split arrays across hardware elements; this doesn’t work if consecutive writes to characters get combined to a word. On Apr 16, 2019, 8:17 PM -0700, Tom Stellard <tstellar at redhat.com>, wrote: > On 04/16/2019 11:38 AM, Neil Ryan via llvm-dev wrote: > > LLVM's optimizer combines stores to consecutive characters into a write of a single word. For instance, if I have char A[4] and I write some static value to each element, these writes would be combine...

Hi Tom, I do not have SVN account, for accessing LLVM. Thanks, Sourabh On Tue 29 Oct, 2019, 9:08 AM Tom Stellard, <tstellar at redhat.com> wrote: > On 10/26/2019 03:39 AM, Sourabh Singh Tomar wrote: > > Hi All, > > > > I recently requested Chris regarding commit access to LLVM. > > He asked me to wait till the GitHub migration completes and then ask in > llvm-dev to get access to GitHub...

...As you can see in the above paragraph, Chris has asked me to find someone to review the code. If there is anyone that would be willing to take the time and look at the code, I would really appreciate it. For your convenience, I have split the code into two patches: http://people.freedesktop.org/~tstellar/llvm/R600.patch http://people.freedesktop.org/~tstellar/llvm/SI.patch R600.patch adds the code required to support the R600 generation of GPUs, and SI.patch adds the code required to support the Southern Islands generation of GPUs. In addition, this code can be found in the branches/R600 branch o...

On 01/09/2020 09:11 AM, Brian Cain wrote: > > > On Thu, Jan 9, 2020 at 12:29 AM Tom Stellard <tstellar at redhat.com <mailto:tstellar at redhat.com>> wrote: > > On 01/08/2020 09:24 AM, Brian Cain wrote: > > Tom, the 9.0.1 final binaries didn't (yet?) make it to the github release page https://github.com/llvm/llvm-project/releases/tag/llvmorg-9.0.1 > > >...

...on of bound_cntl. My understanding is that: 0 => if the source is invalid or disabled, do not write a result 1 => if the source is invalid or disabled, use a 0 instead So the problematic case is where bound_cntl is 0, not when it is 1. -----Original Message----- From: Tom Stellard [mailto:tstellar at redhat.com] Sent: Tuesday, June 13, 2017 6:13 PM To: Matt Arsenault Cc: Connor Abbott; llvm-dev at lists.llvm.org; Kolton, Sam; Sumner, Brian; Pykhtin, Valery Subject: Re: [llvm-dev] Implementing cross-thread reduction in the AMDGPU backend On 06/13/2017 07:33 PM, Matt Arsenault wrote: > &...

...er, Manuel, what's the right way to request/setup something like this? (automatic subscription of the libclc ML to all patches modifying files in llvm/libclc) thank you, Jan Vesely On Sat, Feb 15, 2020 at 12:01 AM Tom Stellard via Phabricator < reviews at reviews.llvm.org> wrote: > tstellar added a comment. > > In D74662#1877571 <https://reviews.llvm.org/D74662#1877571>, @jvesely > wrote: > > > @tstellar , is there a way to make libclc ML an automatic subscriber to > phabricator posted libclc patches? > > > I think you need to ask the phabricator ma...

On 06/13/2017 07:33 PM, Matt Arsenault wrote: > >> On Jun 12, 2017, at 17:23, Tom Stellard <tstellar at redhat.com <mailto:tstellar at redhat.com>> wrote: >> >> On 06/12/2017 08:03 PM, Connor Abbott wrote: >>> On Mon, Jun 12, 2017 at 4:56 PM, Tom Stellard <tstellar at redhat.com <mailto:tstellar at redhat.com>> wrote: >>>> On 06/12/2017 07:15 P...

...ragraph, > Chris has asked me to find someone to review the code. If there is > anyone that would be willing to take the time and look at the code, > I would really appreciate it. For your convenience, I have split the > code into two patches: > > http://people.freedesktop.org/~tstellar/llvm/R600.patch > http://people.freedesktop.org/~tstellar/llvm/SI.patch > > R600.patch adds the code required to support the R600 generation of GPUs, > and SI.patch adds the code required to support the Southern Islands > generation of GPUs. > > In addition, this code can be...

...sked me to find someone to review the code. If there is > > anyone that would be willing to take the time and look at the code, > > I would really appreciate it. For your convenience, I have split the > > code into two patches: > > > > http://people.freedesktop.org/~tstellar/llvm/R600.patch > > http://people.freedesktop.org/~tstellar/llvm/SI.patch > > > > R600.patch adds the code required to support the R600 generation of GPUs, > > and SI.patch adds the code required to support the Southern Islands > > generation of GPUs. > > >...

I'm wondering about the focus on bound_cntl. Any cleared bit in the row_mask or bank_mask will also disable updating the result. Brian -----Original Message----- From: Connor Abbott [mailto:cwabbott0 at gmail.com] Sent: Wednesday, June 14, 2017 6:13 PM To: tstellar at redhat.com Cc: Matt Arsenault; llvm-dev at lists.llvm.org; Kolton, Sam; Sumner, Brian; Pykhtin, Valery Subject: Re: [llvm-dev] Implementing cross-thread reduction in the AMDGPU backend On Wed, Jun 14, 2017 at 5:23 PM, Tom Stellard <tstellar at redhat.com> wrote: > On 06/14/2017 05:05 P...

On 06/14/2017 05:05 PM, Connor Abbott wrote: > On Tue, Jun 13, 2017 at 6:13 PM, Tom Stellard <tstellar at redhat.com> wrote: >> On 06/13/2017 07:33 PM, Matt Arsenault wrote: >>> >>>> On Jun 12, 2017, at 17:23, Tom Stellard <tstellar at redhat.com <mailto:tstellar at redhat.com>> wrote: >>>> >>>> On 06/12/2017 08:03 PM, Connor Abbott w...

...another intermediate format? If the input LLVM IR module was a compute kernel, how would I go about executing it on an AMD GPU? Can I use the APP SDK to load the binary, perhaps through the CAL interfaces? How about the OpenCL binary interface? On Tue, Apr 24, 2012 at 2:52 PM, Tom Stellard <tstellar at gmail.com> wrote: > On Mon, Mar 26, 2012 at 12:50:07PM -0400, Tom Stellard wrote: > > Hi, > > > > We've been working on an LLVM backend for the previous generation of AMD > > GPUs (HD 2XXX - HD 6XXX) and we would like submit it for inclusion in the > > ma...