Displaying 4 results from an estimated 4 matches for "tsflagsfields".
2010 Mar 25
1
[LLVMdev] TSFlagsFields and TSFlagsShifts obsolete?
I think we can get rid of the TSFlagsFields and TSFlagsShifts hack in the InstrInfo TableGen class now.
This seems to work just fine:
class Instruction {
bits<32> TSFlags;
}
class Domain<bits<2> val> {
bits<2> Value = val;
}
def GenericDomain : Domain<0>;
def SSEPackedInt : Domain<1>;
def SSEPa...
2004 Jun 07
0
[LLVMdev] Emitting assembler code
...e question is: how the information about format should be specified
> in .td files? I've tried this:
> But the values of the TSFlags field for did not change.
This one is definitely a tricky one. Take a look at the InstrInfo
tablegen class (in lib/Target/Target.td) and specifically the
TSFlagsFields and TSFlagsShifts lists. In the X86 backend these are
implemented in X86.td.
These specify exactly which fields of the Instruction classes should fill
in which bits of the TSFlags field. The only gross thing is that you
currently have to define a parallel enum or something to access these in
C++...
2004 Jun 07
2
[LLVMdev] Emitting assembler code
Hello,
I'm trying to write assembler code writer, and of course, have new questions.
I'd like the structure my implementation like this:
if (/*binary instruction*/) {
// print destination
O << " = ";
// print first operand
O << opcode;
// print second operand.
}
if (/* unary instruction */ ) {
....
}
if (/*control instruction*/) {
....
2009 May 11
1
[LLVMdev] Instruction categories in the backend
Dear all,
I would like to classify all target specific instructions in a set of categories. The category of each instruction would then be available in the backend.
Just to illustrate what I am trying to do, the first thing I thought about how to achieve this was to group instruction definitions in InstrInfo.td in the order of categories, and to put pseudo instructions in between to mark category