search for: tsflags

Hello LLVM, I'd like to check TSFlags in my AsmBackend code. However AsmBackend objects don't have a reference to MCInstrInfo, which is the only way I've seen to reach TSFlags. A quickie grep shows that none of the existing targets check TSFlags in their AsmBackends. Is there any reason I shouldn't check TSFlags in AsmBa...

I think we can get rid of the TSFlagsFields and TSFlagsShifts hack in the InstrInfo TableGen class now. This seems to work just fine: class Instruction { bits<32> TSFlags; } class Domain<bits<2> val> { bits<2> Value = val; } def GenericDomain : Domain<0>; def SSEPackedInt : Domain<1>; def...

Hello all, I wan to ask, what is exactly the purpose of TSFlags and can it be used for the condition handling in instructions? How can I implement the conditions in the instruction when I don't have access to the Status Register? Best regards, ES -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/piper...

It seems like this code should work with Tablegen, but it generates the error: "error:Invalid TSFlags bit in ADD" Here's the code: =================================== include "llvm/Target/Target.td" def MyInstrInfo : InstrInfo; def MyTarget : Target { // Information about the instructions... let InstructionSet = MyInstrInfo; } def r1 : Register<"r1"> { let...

...Frm : Format<1>; and there are parallel definitions in X86InstrInfo.h: Pseudo = 0, RawFrm = 1, Those definitions are used in codegen, and and TableGen somehow passes the instruction format information to X86GenInstInfo.inc -- specifically, it encodes it in the TSFlags field of the TargetInstrDescriptor class. So the question is: how the information about format should be specified in .td files? I've tried this: class Format<bits<5> val> { bits<5> Value = val; } def F1 : Format<4>; class NMI<string nam> : Instruc...

...no direct access to the Status Register, is it even possible to implement such scenario? On Fri, Jul 10, 2015 at 4:54 PM, Krzysztof Parzyszek < kparzysz at codeaurora.org> wrote: > On 7/10/2015 9:32 AM, Sky Flyer wrote: > >> >> I wan to ask, what is exactly the purpose of TSFlags and can it be used >> for the condition handling in instructions? >> How can I implement the conditions in the instruction when I don't have >> access to the Status Register? >> > > These are target-specific flags that are then stored in the instruction > descri...

On Jan 31, 2013, at 9:27 AM, Sean Silva <silvas at purdue.edu> wrote: > An extra call to resolveReferences after setting the value in the > `let` does fix this, but I'm not sure that it is the right fix. The > attached hackish patch seems to fix up a reduced version of the test > case you gave here (I haven't run a full battery of tests on it, so it > might cause

...are parallel definitions in X86InstrInfo.h: > > Pseudo = 0, > RawFrm = 1, Exactly. > Those definitions are used in codegen, and and TableGen somehow passes the > instruction format information to X86GenInstInfo.inc -- specifically, it > encodes it in the TSFlags field of the TargetInstrDescriptor class. Yup, the TSFlags field is defined to hold TargetSpecific flags of whatever sort you want. Just the thing for holding information about how to print. > So the question is: how the information about format should be specified > in .td files? I've...

...C = 0: no conditions C = 1: zero C = 2: carry C = 4: overflow etc. This way the instruction set would remain small, but it may involve special handling for it to work with the integrated assembler (if the native instruction format is different than what you chose). You could use the TSFlags to indicate for each instruction which condition this instruction can modify. Taking the add again, it could modify all of the three: zero, carry and overflow, but a load could only modify zero (for example, specifics would depend on your target). -Krzysztof -- Qualcomm Innovation Center,...

An extra call to resolveReferences after setting the value in the `let` does fix this, but I'm not sure that it is the right fix. The attached hackish patch seems to fix up a reduced version of the test case you gave here (I haven't run a full battery of tests on it, so it might cause other failures). Jakob, any idea about what the "right" fix is here? -- Sean Silva

Jakob, I think this exactly what's happening. I debugged the resolveReferences for the ADD down into the resolve of TSFlags. It calls VarInit::getFieldInit for the "Val" field of "foo". The code is: Init *VarInit::getFieldInit(Record &R, const RecordVal *RV, const std::string &FieldName) const { if (isa<RecordRecTy>(getType())) if (const RecordVal *Val...

...> C = 2: carry > C = 4: overflow > etc. > > This way the instruction set would remain small, but it may involve > special handling for it to work with the integrated assembler (if the > native instruction format is different than what you chose). > > You could use the TSFlags to indicate for each instruction which condition > this instruction can modify. Taking the add again, it could modify all of > the three: zero, carry and overflow, but a load could only modify zero (for > example, specifics would depend on your target). > > > > -Krzysztof >...

My brief investigation seems to point at this having to do with the let altering the base class, which prevents the usual resolution from occurring (presumably the resolution has already happened for the base). I'll dig into this tomorrow. -- Sean Silva

When I query for installed package on the system, I get following result: # yum list installed openssl Loaded plugins: fastestmirror, tsflags, verify, versionlock Loading mirror speeds from cached hostfile Installed Packages openssl.x86_64 1.0.1e-16.el6_5.4 @updates/$releasever When I try to install already installed package (just playing with yum), I get following result: # yum install openssl Loaded plugins: fastestmirror, tsflags,...

...as follows: def P_256B_VADD : I<0xE1, MRMDestReg, (outs VRP_2048:$dst), (ins VRP_2048:$src1, VRPIM_2048:$src2),"P_256B_VADD\t{$src1, $src2, $dst|$dst, $src1, $src2}", [(set VRP_2048:$dst, (add (v64i32 VRP_2048:$src1), (v64i32 VRP_2048:$src2)))]>, TA; so i defined; bool HasTA = TSFlags & X86II::TA; in x86MCCodeEmitter.cpp then used this condition; if(HasTA) ++SrcRegNum; now getting no error. please tell me whether my method is correct? Also please confirm this whether i need to make changes in MC framework to emit binary code of my vector instructions. So far i made...

...t // according to the right size for the instruction. Some instructions // (SSE4a extrq and insertq) have two trailing immediates. while (CurOp != NumOps && NumOps - CurOp <= 2) { EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags), CurByte, OS, Fixups); } here CurOp=2 !=NumOps=3 && 3-2<=2 so while condition is satisfied and it goes to emitimmediate which is wrong and there prints error message. Since, there are no immediate involved in instruction, it should not...

...VRP_2048:$dst), (ins >> VRP_2048:$src1, VRPIM_2048:$src2),"P_256B_VADD\t{$src1, $src2, >> $dst|$dst, $src1, $src2}", [(set VRP_2048:$dst, (add (v64i32 >> VRP_2048:$src1), (v64i32 VRP_2048:$src2)))]>, TA; >> >> so i defined; >> >> bool HasTA = TSFlags & X86II::TA; in x86MCCodeEmitter.cpp >> >> then used this condition; >> >> if(HasTA) >> ++SrcRegNum; >> >> now getting no error. >> >> please tell me whether my method is correct? Also please confirm this >> whether i need to mak...

I was getting same error when i keep both EVEX/EVEX_4V and TA. So, i restored my original instructions and for that i have to include bool HasTA = TSFlags & X86II::TA; in x86MCCodeEmitter.cpp then used this condition; if(HasTA) ++SrcRegNum; in order to emit binary correctly. Is it right? On Tue, Sep 5, 2017 at 5:45 AM, Craig Topper <craig.topper at gmail.com> wrote: > Put the TA's back. EVEX/EVEX_4V does not replace TA. T...

...PIM_2048:$src2),"P_256B_VADD\t{$src1, $src2, >>>> $dst|$dst, $src1, $src2}", [(set VRP_2048:$dst, (add (v64i32 >>>> VRP_2048:$src1), (v64i32 VRP_2048:$src2)))]>, TA; >>>> >>>> so i defined; >>>> >>>> bool HasTA = TSFlags & X86II::TA; in x86MCCodeEmitter.cpp >>>> >>>> then used this condition; >>>> >>>> if(HasTA) >>>> ++SrcRegNum; >>>> >>>> now getting no error. >>>> >>>> please tell me whether my me...

...rc1, $src2}", [(set VRP_2048:$dst, (add (v64i32 >>>>>>>> VRP_2048:$src1), (v64i32 VRP_2048:$src2)))]>, TA; >>>>>>>> >>>>>>>> so i defined; >>>>>>>> >>>>>>>> bool HasTA = TSFlags & X86II::TA; in x86MCCodeEmitter.cpp >>>>>>>> >>>>>>>> then used this condition; >>>>>>>> >>>>>>>> if(HasTA) >>>>>>>> ++SrcRegNum; >>>>>>>> >&...